From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753125AbbCJOfU (ORCPT ); Tue, 10 Mar 2015 10:35:20 -0400 Received: from service87.mimecast.com ([91.220.42.44]:44335 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752742AbbCJOfR convert rfc822-to-8bit (ORCPT ); Tue, 10 Mar 2015 10:35:17 -0400 Message-ID: <54FF0120.1070205@arm.com> Date: Tue, 10 Mar 2015 14:35:12 +0000 From: Sudeep Holla User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Borislav Petkov CC: Sudeep Holla , "linux-kernel@vger.kernel.org" , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andre Przywara , "x86@kernel.org" Subject: Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure References: <1424715265-21407-1-git-send-email-sudeep.holla@arm.com> <1425470416-20691-1-git-send-email-sudeep.holla@arm.com> <20150304122720.GD3663@pd.tnic> <20150305081640.GA3817@pd.tnic> <54F821D8.4030605@arm.com> <20150310113707.GE3535@pd.tnic> <54FEDB3F.4080007@arm.com> <54FEFE1E.1070901@arm.com> <20150310142627.GF3535@pd.tnic> In-Reply-To: <20150310142627.GF3535@pd.tnic> X-OriginalArrivalTime: 10 Mar 2015 14:35:12.0368 (UTC) FILETIME=[6A9FF700:01D05B3F] X-MC-Unique: 115031014351408801 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/03/15 14:26, Borislav Petkov wrote: > On Tue, Mar 10, 2015 at 02:22:22PM +0000, Sudeep Holla wrote: >> I was able to reproduce this and now I realise I had CONFIG_AMD_NB >> disabled in my config earlier which hid this issue previously, sorry >> for that. >> >> The below patch fixed the issue on my Intel i7 box. I can post this >> separately if required. >> >> Regards, >> Sudeep >> >> From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001 >> From: Sudeep Holla >> Date: Tue, 10 Mar 2015 13:49:58 +0000 >> Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel >> processors >> >> The private pointer provided by the cacheinfo is used to implement >> the AMD L3 cache specific attributes using the northbridge pointer >> obtained through cpuid4 registers. However, it's populated even on >> Intel processors for Level 3 cache. This results in failure of > > Do we need it populated on Intel? > > Because if not, we can leave it NULL there and do only > > if (this_leaf->level < 3 || !nb) > return NULL; > Yes we can do that. I leave that too you guys. I don't know the exact reason why cpuid4_cache_lookup_regs is populating struct amd_northbridge *nb in struct _cpuid4_info_reg My initial assumption was that it will be NULL for Intel processors and hence I assigned cacheinfo->priv to nb pointer unconditionally. So I don't have any strong opinion here. Regards, Sudeep