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Fri, 17 Apr 2026 09:04:20 -0700 (PDT) X-Received: by 2002:a05:6a00:4b01:b0:82f:390a:69df with SMTP id d2e1a72fcca58-82f8c8d616emr3650474b3a.35.1776441860173; Fri, 17 Apr 2026 09:04:20 -0700 (PDT) Received: from [10.206.105.200] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8e9d6adbsm3256264b3a.18.2026.04.17.09.04.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Apr 2026 09:04:19 -0700 (PDT) Message-ID: <54a670dc-4792-13eb-4240-29bc3dcdb33a@oss.qualcomm.com> Date: Fri, 17 Apr 2026 21:34:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Vishnu Reddy Subject: Re: [PATCH 08/11] media: iris: Add power sequence for Glymur To: Konrad Dybcio , Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio , Stefan Schmidt , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev References: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> <20260414-glymur-v1-8-7d3d1cf57b16@oss.qualcomm.com> <1de1a366-a325-428e-9dcc-1333bb85ed82@oss.qualcomm.com> Content-Language: en-US In-Reply-To: <1de1a366-a325-428e-9dcc-1333bb85ed82@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 4bZjvDF_1w0dvESB5LT_jTl05p2CgvEJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDE2MSBTYWx0ZWRfX/9CQCPIm/cJ8 NFNdM2RjTDW5Lg94fh0ybLNuAMKqK2Y/UG3PR8nUejS8Se+VAbV5cB4nGgiAgCeaqj82s/kNVSf n3YuJIKGJM2iFCHUifrHWteYbQ0zafL9n2KJgnwSvMrT8vKSVyq7C3EoN3Y2cNjFwD1pNCJf800 HoPi+da6Xy8225pCytM3so7GRRsfhX6r058AaWA0X+ipYzQ6IlaSAkidLk2YVO0sgI4IOJp6iKK fdPW6TuWuPkta/Ft6LWX8rFn6DZXx7aH8tmR8iifWoC11/VG9ammSxnTj/2EsrK5BSX2PvA6DLG GPvWeqA9wEPbMxdA1ao938hpWXmq25GP9g17ECJp4fnu9KodFxBA4dHRkGUn13/eXLmCs/rYLO5 v1FoxGSQP0OM59QFpuFVvr9BB8By71y60hVBJwsqmFcLPmnl6eTOstiVq8aTHo8N3cwlbBt1h7E vsMqKFh5uU1Z2+JeZ2w== X-Authority-Analysis: v=2.4 cv=X+Fi7mTe c=1 sm=1 tr=0 ts=69e25a11 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=bWAOSzAfB_7jWjvagxkA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: 4bZjvDF_1w0dvESB5LT_jTl05p2CgvEJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-17_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170161 On 4/14/2026 3:19 PM, Konrad Dybcio wrote: > On 4/14/26 7:00 AM, Vishnu Reddy wrote: >> Add power sequence hooks for controller, vcodec and vcodec1. reuse the >> existing code where ever is possible. add vcodec1 power on and off code >> separately which has different power domains and clocks. >> >> Signed-off-by: Vishnu Reddy >> --- >> .../platform/qcom/iris/iris_platform_common.h | 9 ++ >> drivers/media/platform/qcom/iris/iris_vpu3x.c | 123 +++++++++++++++++++++ >> drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + >> .../platform/qcom/iris/iris_vpu_register_defines.h | 7 ++ >> 4 files changed, 140 insertions(+) >> >> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h >> index 30e9d4d288c6..e3c1aff770dd 100644 >> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h >> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h >> @@ -61,6 +61,9 @@ enum platform_clk_type { >> IRIS_VPP0_HW_CLK, >> IRIS_VPP1_HW_CLK, >> IRIS_APV_HW_CLK, >> + IRIS_AXI_VCODEC1_CLK, >> + IRIS_VCODEC1_CLK, >> + IRIS_VCODEC1_FREERUN_CLK, >> }; >> >> struct platform_clk_data { >> @@ -208,6 +211,12 @@ enum platform_pm_domain_type { >> IRIS_CTRL_POWER_DOMAIN, >> IRIS_VCODEC_POWER_DOMAIN, >> IRIS_VPP0_HW_POWER_DOMAIN, >> + /* >> + * On Glymur, vcodec1 power domain is at the same index in pd_devs[] >> + * as IRIS_VPP0_HW_POWER_DOMAIN. Alias it so that the Glymur power >> + * domain table is indexed correctly. >> + */ >> + IRIS_VCODEC1_POWER_DOMAIN = IRIS_VPP0_HW_POWER_DOMAIN, > This feels really fragile.. I'm thinking to add wrapper and use the power domain name to find the index from the platform data instead of using the enum values. I'll try this if that works. > [...] > >> +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) >> +{ >> + u32 value, pwr_status; >> + >> + value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); >> + pwr_status = value & BIT(4); >> + >> + return pwr_status ? false : true; > return !pwr_status Ack. Thanks, Vishnu Reddy. > Konrad