From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753635AbbCKPor (ORCPT ); Wed, 11 Mar 2015 11:44:47 -0400 Received: from service87.mimecast.com ([91.220.42.44]:49199 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751645AbbCKPop convert rfc822-to-8bit (ORCPT ); Wed, 11 Mar 2015 11:44:45 -0400 Message-ID: <550062E7.3090603@arm.com> Date: Wed, 11 Mar 2015 15:44:39 +0000 From: Sudeep Holla User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Borislav Petkov CC: Sudeep Holla , "linux-kernel@vger.kernel.org" , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andre Przywara , "x86@kernel.org" Subject: Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure References: <1424715265-21407-1-git-send-email-sudeep.holla@arm.com> <1425470416-20691-1-git-send-email-sudeep.holla@arm.com> <20150304122720.GD3663@pd.tnic> <20150305081640.GA3817@pd.tnic> <54F821D8.4030605@arm.com> <20150310113707.GE3535@pd.tnic> <54FEDB3F.4080007@arm.com> <54FEFE1E.1070901@arm.com> <20150310142627.GF3535@pd.tnic> <54FF0120.1070205@arm.com> <20150311133647.GB4464@pd.tnic> In-Reply-To: <20150311133647.GB4464@pd.tnic> X-OriginalArrivalTime: 11 Mar 2015 15:44:39.0673 (UTC) FILETIME=[48F1FE90:01D05C12] X-MC-Unique: 115031115444201301 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Boris, On 11/03/15 13:36, Borislav Petkov wrote: > On Tue, Mar 10, 2015 at 02:35:12PM +0000, Sudeep Holla wrote: >> My initial assumption was that it will be NULL for Intel processors >> and hence I assigned cacheinfo->priv to nb pointer unconditionally. So >> I don't have any strong opinion here. > > Right, we need the NB descriptor on AMD to do L3-specific operations, > see amd_l3_disable_index() for an example. > > IOW, I ended up committing this: > It looks fine to me except one unwanted/incorrect line in the commit log as mentioned below. I gave it a spin on my i7 box and it works. Thanks for the fix up. > --- > From: Sudeep Holla > Date: Wed, 11 Mar 2015 11:54:29 +0100 > Subject: [PATCH] x86/cacheinfo: Fix cache_get_priv_group() for Intel > processors > > The private pointer provided by the cacheinfo code is used to implement > the AMD L3 cache-specific attributes using a pointer to the northbridge > descriptor. It is needed for performing L3-specific operations and for > that we need a couple of PCI devices and other service information, all > contained in the northbridge descriptor. > > However, it's populated even on Intel processors for an L3 cache. After testing this patch, I think I had misunderstood before and it's not populated on Intel processors, so you can drop the line above. Regards, Sudeep