From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE9DC2701DC; Fri, 29 Aug 2025 14:06:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756476369; cv=none; b=nE838hVwasi1KB/5JrIksx8wSnVkhITmk94k0xhIjiNYx1rPogPROpZ5gastemJGCzruWXYr7LKcfIFmZFsTxW58XwyImARLb5VZg4E5RXnHaP8tWJPkFmttjhPxF5YuKfonD9JKpfDsiXsdpdFGnezJ1QZyrxMrd4aXKEiqqe0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756476369; c=relaxed/simple; bh=5hnfrxB59btF5GVW6Vc7xXSqfEVv47osUlR/KT5zvJc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=MzqX9sXdnnO1vMMa9uPDK3WZ6teKM4CeKsohU48o/VBViV+mz9dJ/ojerbGrNdv/QQ5xe29bWGdeNuf9EVj1ojOQCiRI/dCKKmssgoPuan3YyGvkEtawNCQ/lOos4XoDzFSTT34I4boY2gYqkfQVmRBSrp67E70DMPdu6kZBVyk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Uhf2/Hoi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Uhf2/Hoi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 63CF0C4CEF0; Fri, 29 Aug 2025 14:06:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756476368; bh=5hnfrxB59btF5GVW6Vc7xXSqfEVv47osUlR/KT5zvJc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Uhf2/HoiXGKYEqu/pkUaMb2gMLZ+iBw5kivrOV03qQ9PCcUoxKw51pzRvZEYvJ/ab knEgYDfSXfewnVQYciMw0Mw0dVOcaC6gB85gV6iuC991zGcd2Palbsg+OFI81+InTD jcXXpoPWlB/uIrVzYh5CGlL72Os0fwEKfHZDzS09Ft8ZUR9Ee+C2WABDq9UzEwKGSR rsIPmQyUUMnidYFGTy/HXIlkXq5A3lIO0BKhqiOQvOYg2yC18ZJdiVtm59zWMQGVzd ZCqrjgLZj4cSKK8h69DA1Emr5ISXUPR9TjJlXarSrabTK8Eu0CyBDBHkom9rteQMAF +KDIdWBUpNRpA== Message-ID: <5502f52d-d302-4479-93b8-1da47731cf1d@kernel.org> Date: Fri, 29 Aug 2025 16:06:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 8/9] media: chips-media: wave6: Add Wave6 control driver To: Nas Chung , mchehab@kernel.org, hverkuil@xs4all.nl, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, jackson.lee@chipsnmedia.com, lafley.kim@chipsnmedia.com, Ming Qian References: <20250829084649.359-1-nas.chung@chipsnmedia.com> <20250829084649.359-9-nas.chung@chipsnmedia.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 29/08/2025 10:46, Nas Chung wrote: > + > +static void wave6_vpu_load_firmware(const struct firmware *fw, void *context) > +{ > + struct wave6_vpu_device *vpu = context; > + > + guard(mutex)(&vpu->lock); Why? How could this be called in parallel, before the probe? > + > + if (!fw || !fw->data) { > + dev_err(vpu->dev, "No firmware.\n"); > + return; > + } > + > + if (!vpu->fw_available) > + goto exit; > + > + if (fw->size + W6_EXTRA_CODE_BUF_SIZE > wave6_vpu_get_code_buf_size(vpu)) { > + dev_err(vpu->dev, "firmware size (%ld > %zd) is too big\n", > + fw->size, vpu->code_buf.size); > + vpu->fw_available = false; > + goto exit; > + } > + > + memcpy(vpu->code_buf.vaddr, fw->data, fw->size); > + > + vpu->get_vpu = wave6_vpu_get; > + vpu->put_vpu = wave6_vpu_put; > + vpu->req_work_buffer = wave6_vpu_require_work_buffer; > + of_platform_populate(vpu->dev->of_node, NULL, NULL, vpu->dev); > + > +exit: > + release_firmware(fw); > +} > + > +static int wave6_vpu_probe(struct platform_device *pdev) > +{ > + struct device_node *np; > + struct wave6_vpu_device *vpu; > + const struct wave6_vpu_resource *res; > + int ret; > + > + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); > + if (ret < 0) { > + dev_err(&pdev->dev, "dma_set_mask_and_coherent failed: %d\n", ret); > + return ret; > + } > + > + res = of_device_get_match_data(&pdev->dev); > + if (!res) > + return -ENODEV; > + > + vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL); > + if (!vpu) > + return -ENOMEM; > + > + ret = devm_mutex_init(&pdev->dev, &vpu->lock); > + if (ret) > + return ret; > + > + atomic_set(&vpu->core_count, 0); > + INIT_LIST_HEAD(&vpu->work_buffers); > + dev_set_drvdata(&pdev->dev, vpu); > + vpu->dev = &pdev->dev; > + vpu->res = res; > + vpu->reg_base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(vpu->reg_base)) > + return PTR_ERR(vpu->reg_base); > + > + ret = devm_clk_bulk_get_all(&pdev->dev, &vpu->clks); > + if (ret < 0) { > + dev_warn(&pdev->dev, "unable to get clocks: %d\n", ret); You need to handle deferred probe. > + ret = 0; > + } > + vpu->num_clks = ret; Best regards, Krzysztof