From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756654AbbCMQv3 (ORCPT ); Fri, 13 Mar 2015 12:51:29 -0400 Received: from mail-bl2on0102.outbound.protection.outlook.com ([65.55.169.102]:1720 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751491AbbCMQvZ (ORCPT ); Fri, 13 Mar 2015 12:51:25 -0400 X-WSS-ID: 0NL5THI-07-4CI-02 X-M-MSG: Message-ID: <55031585.2030908@amd.com> Date: Fri, 13 Mar 2015 11:51:17 -0500 From: Joel Schopp User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: , CC: Tony Luck , Borislav Petkov , "Thomas Gleixner" , Ingo Molnar , "H. Peter Anvin" , , Subject: Re: [PATCH v2] mce: use safe MSR accesses References: <1426262619-5016-1-git-send-email-jesse.larrew@amd.com> In-Reply-To: <1426262619-5016-1-git-send-email-jesse.larrew@amd.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.180.168.240] X-EOPAttributedMessage: 0 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=Joel.Schopp@amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;BMV:1;SFV:NSPM;SFS:(10019020)(6009001)(428002)(199003)(377454003)(51704005)(189002)(479174004)(24454002)(76176999)(87266999)(54356999)(99136001)(50986999)(65816999)(50466002)(23746002)(64126003)(36756003)(46102003)(106466001)(105586002)(101416001)(47776003)(19580395003)(83506001)(19580405001)(65806001)(65956001)(87936001)(77156002)(62966003)(86362001)(2950100001)(77096005)(53416004)(92566002)(117636001)(62816006);DIR:OUT;SFP:1102;SCL:1;SRVR:BN3PR0201MB1044;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR0201MB1044;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR0201MB0931; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5002009)(5005006);SRVR:BN3PR0201MB1044;BCL:0;PCL:0;RULEID:;SRVR:BN3PR0201MB1044; X-Forefront-PRVS: 05143A8241 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2015 16:51:20.6829 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR0201MB1044 X-OriginatorOrg: amd4.onmicrosoft.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/13/2015 11:03 AM, jesse.larrew@amd.com wrote: > From: Jesse Larrew > > Certain MSRs are only relevant to a kernel in host mode, and kvm had > chosen not to implement these MSRs at all for guests. If a guest kernel > ever tried to access these MSRs, the result was a general protection > fault. > > KVM will be separately patched to return 0 when these MSRs are read, > and this patch ensures that MSR accesses are tolerant of exceptions. > > Signed-off-by: Jesse Larrew > --- > arch/x86/kernel/cpu/mcheck/mce.c | 11 +++-------- > 1 file changed, 3 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c > index 61a9668ce..2737ced 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce.c > +++ b/arch/x86/kernel/cpu/mcheck/mce.c > @@ -1540,7 +1540,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) > if (c->x86 == 0x15 && > (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { > int i; > - u64 val, hwcr; > + u64 hwcr; > bool need_toggle; > u32 msrs[] = { > 0x00000413, /* MC4_MISC0 */ > @@ -1556,13 +1556,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) > wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); > > for (i = 0; i < ARRAY_SIZE(msrs); i++) { > - rdmsrl(msrs[i], val); > - > - /* CntP bit set? */ > - if (val & BIT_64(62)) { > - val &= ~BIT_64(62); > - wrmsrl(msrs[i], val); > - } > + /* Clear CntP bit safely */ > + msr_clear_bit(msrs[i], 62); > } > > /* restore old settings */ I like it. Reviewed-by: Joel Schopp