From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751876AbbCTP7n (ORCPT ); Fri, 20 Mar 2015 11:59:43 -0400 Received: from mail-by2on0139.outbound.protection.outlook.com ([207.46.100.139]:8512 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750823AbbCTP7j (ORCPT ); Fri, 20 Mar 2015 11:59:39 -0400 X-WSS-ID: 0NLIPRA-08-YER-02 X-M-MSG: Message-ID: <550C43E5.4090302@amd.com> Date: Fri, 20 Mar 2015 10:59:33 -0500 From: Aravind Gopalakrishnan User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: "Luck, Tony" , Borislav Petkov CC: "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "slaoub@gmail.com" , "luto@amacapital.net" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "linux-edac@vger.kernel.org" Subject: Re: [PATCH] x86, mce, severities: Add AMD severities function References: <1426526164-3806-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <20150317102048.GG19645@pd.tnic> <5508756A.1090908@amd.com> <20150317184441.GI19645@pd.tnic> <3908561D78D1C84285E8C5FCA982C28F32A234ED@ORSMSX114.amr.corp.intel.com> <20150319092953.GB10860@pd.tnic> <550ADFFD.2090708@amd.com> <20150319155345.GE11715@pd.tnic> <550AF743.8070906@amd.com> <3908561D78D1C84285E8C5FCA982C28F32A23E9C@ORSMSX114.amr.corp.intel.com> In-Reply-To: <3908561D78D1C84285E8C5FCA982C28F32A23E9C@ORSMSX114.amr.corp.intel.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.180.168.240] X-EOPAttributedMessage: 0 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=Aravind.Gopalakrishnan@amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;BMV:1;SFV:NSPM;SFS:(10019020)(6009001)(428002)(51704005)(479174004)(199003)(164054003)(377454003)(189002)(59896002)(64126003)(2950100001)(101416001)(23676002)(120886001)(65956001)(46102003)(33656002)(65816999)(92566002)(80316001)(65806001)(93886004)(36756003)(62966003)(77156002)(105586002)(87266999)(77096005)(54356999)(76176999)(83506001)(50986999)(87936001)(50466002)(106466001)(47776003)(86362001);DIR:OUT;SFP:1102;SCL:1;SRVR:BLUPR02MB405;H:atltwp02.amd.com;FPR:;SPF:None;MLV:sfv;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR02MB405; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5002010)(5005006);SRVR:BLUPR02MB405;BCL:0;PCL:0;RULEID:;SRVR:BLUPR02MB405; X-Forefront-PRVS: 05214FD68E X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2015 15:59:36.1048 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR02MB405 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/19/2015 12:15 PM, Luck, Tony wrote: >>> It would be best if what Tony suggested comes ontop of your patch with >>> his Suggested-by: tag. This ordering should be also the easiest wrt >>> functionality and bisectability. >>> >>> >> Ok, I'll have it ready and send out a V2 by tomorrow if there are no >> other comments/reviews. > Fame & glory ... whatever. Just be sure to make the _intel() and _amd() > severity functions "static" ... so you'll need something like this in mce-severity.c > > void mce_vendor_severity_init(void) > { > .... assign mce_severity here > } > > Ok, Here's how I have it currently: void __init mcheck_vendor_init_severity(void) { struct cpuinfo_x86 *c = &boot_cpu_data; switch (c->x86_vendor) { case X86_VENDOR_INTEL: mce_severity = mce_severity_intel; break; case X86_VENDOR_AMD: mce_severity = mce_severity_amd; break; default: break; } } And I call this from mcheck_init(). I tested the above bits on AMD and the severities grading works fine. Should we also come up with a '_default' function to assign to mce_severity function pointer? Something like- static int mce_severity_default(struct mce *m, int tolerant, char **msg, bool is_excp) { pr_err("CPU#%d: No vendor specific severities grader assigned. Implementing default grader\n", smp_processor_id()); if (m->status & MCI_STATUS_PCC || m->status & MCI_STATUS_OVER) return MCE_PANIC_SEVERITY; if (m->status & MCI_STATUS_UC) return MCE_UC_SEVERITY; return MCE_KEEP_SEVERITY; } int (*mce_severity) (struct mce *m, int tolerant, char **msg, bool is_excp) = mce_severity_default; How much of grading should '_default' do if at all? Thanks, -Aravind.