From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756472AbbDGNcQ (ORCPT ); Tue, 7 Apr 2015 09:32:16 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:28813 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754848AbbDGNcJ convert rfc822-to-8bit (ORCPT ); Tue, 7 Apr 2015 09:32:09 -0400 X-AuditID: cbfee68d-f79266d0000049c9-12-5523dc5677db MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 8BIT Message-id: <5523DC56.6030108@samsung.com> Date: Tue, 07 Apr 2015 22:32:06 +0900 From: Inki Dae User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130803 Thunderbird/17.0.8 To: Krzysztof Kozlowski Cc: Jingoo Han , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , David Airlie , Kukjin Kim , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fbdev@vger.kernel.org, Marek Szyprowski , Andrzej Hajda , Javier Martinez Canillas , stable@vger.kernel.org Subject: Re: [RFT PATCHv2] drm/exynos: Enable DP clock to fix display on Exynos5250 and other References: <1427472488-21454-1-git-send-email-k.kozlowski@samsung.com> In-reply-to: <1427472488-21454-1-git-send-email-k.kozlowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPIsWRmVeSWpSXmKPExsWyRsSkQDfsjnKowePn4ha31p1jteg9d5LJ 4srX92wWR38XWFxeeInV4sW9iywWr18YWvQ/fs1scbbpDbvFpsfXWC1O9H1gtbi8aw6bxYzz +5gs1h65y26xYOMjRosZk1+yOQh4/H1+ncVj06pONo/t3x6wetzvPs7ksXlJvUffllWMHp83 yQWwR3HZpKTmZJalFunbJXBlTGt6wF7QrFfx4uFX5gbG56pdjJwcEgImElsPtLBA2GISF+6t Z+ti5OIQEljKKLGz4SIjTNGzXWuYIBKLGCUa3i1mBUnwCghK/Jh8D6ybWUBdYtK8RcwQtojE lxub2CBsbYllC1+DxYUE7jNKvF6sAtGrJTGt5wRYnEVAVeLUujawOWxA9sQV98F6RQXCJF68 2gVWIyJgKHFw93YmiJn7WCR6d+qB2MIC8RIL53azQMx3l3j57ghYDaeAh0T/+9esIEdLCMzl kFix9xY7xDIBiW+TDwE1cAAlZCU2HWCGeFJS4uCKGywTGMVnIXltFpLXZiF5bRaS1xYwsqxi FE0tSC4oTkovMtQrTswtLs1L10vOz93ECEwHp/89693BePuA9SFGAQ5GJR5eBjnlUCHWxLLi ytxDjKZAF01klhJNzgcmnbySeENjMyMLUxNTYyNzSzMlcV5FqZ/BQgLpiSWp2ampBalF8UWl OanFhxiZODilGhjLs3N//xf7y3ii/onwvTfuThYzz3s/LSx/1tI+/V5aVcgqs0cep/m42fMb Z4SdT2d7virg0JKZu7ka/ayef2aPyJeUuWCj7yz8/GjD7QzND+zzgo/rliRk/5p/mN+w0J/l /KfmRTxLT2+352FRNQh/oxNiyHSjovYp/24Rm211d2oPmbhUTlJiKc5INNRiLipOBAAmXN6P AgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPKsWRmVeSWpSXmKPExsVy+t9jAd2wO8qhBis38VrcWneO1aL33Ekm iytf37NZHP1dYHF54SVWixf3LrJYvH5haNH/+DWzxdmmN+wWmx5fY7U40feB1eLyrjlsFjPO 72OyWHvkLrvFgo2PGC1mTH7J5iDg8ff5dRaPTas62Ty2f3vA6nG/+ziTx+Yl9R59W1Yxenze JBfAHtXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6DrlpkD dLuSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMeP4im+MBY91K44/3M/e wHhctYuRk0NCwETi2a41TBC2mMSFe+vZuhi5OIQEFjFKNLxbzAqS4BUQlPgx+R5LFyMHB7OA vMSRS9kgYWYBdYlJ8xYxg9hCAvcZJV4vVoEo15KY1nMCLM4ioCpxal0bC4jNBmRPXHGfDcQW FQiTePFqF1iNiIChxMHd25kgZu5jkejdqQdiCwvESyyc280CMd9d4uW7I2A1nAIeEv3vX7NO YBSYheS6WQjXzUJy3QJG5lWMoqkFyQXFSem5hnrFibnFpXnpesn5uZsYwYnjmdQOxpUNFocY BTgYlXh4GeSUQ4VYE8uKK3MPMUpwMCuJ8MqeBgrxpiRWVqUW5ccXleakFh9iNAV6biKzlGhy PjCp5ZXEGxqbmBlZGpkbWhgZmyuJ887RlQsVEkhPLEnNTk0tSC2C6WPi4JRqYLQ1ZP257v0L xi+b9c2/XYl+J+tcoXIiSPenX+X3mNpLuwNPRTV95mKWsvyg3vC+/8Ak9fiyZcu8y46wLfKz ftanO0Pg02bex892d/k2n2a3Vbeb8HFzHVdo25TZ2+6XLy/Km3eyX+eudV5hi7zQttvv1cJv uj979/v+zLLTU/83Pi6tfPhS+JUSS3FGoqEWc1FxIgCzWTAhMgMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015년 03월 28일 01:08, Krzysztof Kozlowski wrote: > After adding display power domain for Exynos5250 in commit > 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") the > display on Chromebook Snow and others stopped working after boot. > > The reason for this suggested Andrzej Hajda: the DP clock was disabled. > This clock is required by Display Port and is enabled by bootloader. > However when FIMD driver probing was deferred, the display power domain > was turned off. This effectively reset the value of DP clock enable > register. Applied. Thanks, Inki Dae > > When exynos-dp is later probed, the clock is not enabled and display is > not properly configured: > > exynos-dp 145b0000.dp-controller: Timeout of video streamclk ok > exynos-dp 145b0000.dp-controller: unable to config video > > Signed-off-by: Krzysztof Kozlowski > Reported-by: Javier Martinez Canillas > Fixes: 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") > Cc: > > --- > > This should fix issue reported by Javier [1][2]. > > Tested on Chromebook Snow (Exynos 5250). More testing would be great, > especially on other Exynos 5xxx products. > > [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/43889 > [2] http://thread.gmane.org/gmane.linux.ports.arm.kernel/400290 > > Changes since v1: > 1. Added missing exynos_drm_fimd.h. > --- > drivers/gpu/drm/exynos/exynos_dp_core.c | 10 ++++++++++ > drivers/gpu/drm/exynos/exynos_drm_fimd.c | 19 +++++++++++++++++++ > drivers/gpu/drm/exynos/exynos_drm_fimd.h | 15 +++++++++++++++ > include/video/samsung_fimd.h | 6 ++++++ > 4 files changed, 50 insertions(+) > create mode 100644 drivers/gpu/drm/exynos/exynos_drm_fimd.h > > diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c > index bf17a60b40ed..1dbfba58f909 100644 > --- a/drivers/gpu/drm/exynos/exynos_dp_core.c > +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c > @@ -32,10 +32,16 @@ > #include > > #include "exynos_dp_core.h" > +#include "exynos_drm_fimd.h" > > #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \ > connector) > > +static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp) > +{ > + return to_exynos_crtc(dp->encoder->crtc); > +} > + > static inline struct exynos_dp_device * > display_to_dp(struct exynos_drm_display *d) > { > @@ -1070,6 +1076,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp) > } > } > > + fimd_dp_clock_enable(dp_to_crtc(dp), true); > + > clk_prepare_enable(dp->clock); > exynos_dp_phy_init(dp); > exynos_dp_init_dp(dp); > @@ -1094,6 +1102,8 @@ static void exynos_dp_poweroff(struct exynos_dp_device *dp) > exynos_dp_phy_exit(dp); > clk_disable_unprepare(dp->clock); > > + fimd_dp_clock_enable(dp_to_crtc(dp), false); > + > if (dp->panel) { > if (drm_panel_unprepare(dp->panel)) > DRM_ERROR("failed to turnoff the panel\n"); > diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c > index c300e22da8ac..bdf0818dc8f5 100644 > --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c > +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c > @@ -32,6 +32,7 @@ > #include "exynos_drm_fbdev.h" > #include "exynos_drm_crtc.h" > #include "exynos_drm_iommu.h" > +#include "exynos_drm_fimd.h" > > /* > * FIMD stands for Fully Interactive Mobile Display and > @@ -1231,6 +1232,24 @@ static int fimd_remove(struct platform_device *pdev) > return 0; > } > > +void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) > +{ > + struct fimd_context *ctx = crtc->ctx; > + u32 val; > + > + /* > + * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE > + * clock. On these SoCs the bootloader may enable it but any > + * power domain off/on will reset it to disable state. > + */ > + if (ctx->driver_data != &exynos5_fimd_driver_data) > + return; > + > + val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; > + writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); > +} > +EXPORT_SYMBOL_GPL(fimd_dp_clock_enable); > + > struct platform_driver fimd_driver = { > .probe = fimd_probe, > .remove = fimd_remove, > diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.h b/drivers/gpu/drm/exynos/exynos_drm_fimd.h > new file mode 100644 > index 000000000000..b4fcaa568456 > --- /dev/null > +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.h > @@ -0,0 +1,15 @@ > +/* > + * Copyright (c) 2015 Samsung Electronics Co., Ltd. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > + > +#ifndef _EXYNOS_DRM_FIMD_H_ > +#define _EXYNOS_DRM_FIMD_H_ > + > +extern void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable); > + > +#endif /* _EXYNOS_DRM_FIMD_H_ */ > diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h > index a20e4a3a8b15..847a0a2b399c 100644 > --- a/include/video/samsung_fimd.h > +++ b/include/video/samsung_fimd.h > @@ -436,6 +436,12 @@ > #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) > #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) > > +/* Display port clock control */ > +#define DP_MIE_CLKCON 0x27c > +#define DP_MIE_CLK_DISABLE 0x0 > +#define DP_MIE_CLK_DP_ENABLE 0x2 > +#define DP_MIE_CLK_MIE_ENABLE 0x3 > + > /* Notes on per-window bpp settings > * > * Value Win0 Win1 Win2 Win3 Win 4 >