From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031118AbbD1WiD (ORCPT ); Tue, 28 Apr 2015 18:38:03 -0400 Received: from mga09.intel.com ([134.134.136.24]:64622 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031071AbbD1WiB (ORCPT ); Tue, 28 Apr 2015 18:38:01 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,666,1422950400"; d="scan'208";a="720727137" Message-ID: <55400BC8.6080204@intel.com> Date: Tue, 28 Apr 2015 15:38:00 -0700 From: Dave Hansen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: "Kirill A. Shutemov" , Andy Lutomirski CC: Linus Torvalds , Andrew Morton , Mel Gorman , Rik van Riel , linux-kernel@vger.kernel.org, linux-mm@kvack.org, x86@kernel.org Subject: Re: PCID and TLB flushes (was: [GIT PULL] kdbus for 4.1-rc1) References: <20150428221553.GA5770@node.dhcp.inet.fi> In-Reply-To: <20150428221553.GA5770@node.dhcp.inet.fi> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/28/2015 03:15 PM, Kirill A. Shutemov wrote: > On Tue, Apr 28, 2015 at 01:42:10PM -0700, Andy Lutomirski wrote: >> At some point, I'd like to implement PCID on x86 (if no one beats me >> to it, and this is a low priority for me), which will allow us to skip >> expensive TLB flushes while context switching. I have no idea whether >> ARM can do something similar. > > I talked with Dave about implementing PCID and he thinks that it will be > net loss. TLB entries will live longer and it means we would need to trigger > more IPIs to flash them out when we have to. Cost of IPIs will be higher > than benifit from hot TLB after context switch. > > Do you have different expectations? Kirill, I think Andy is asking about something different that what you and I talked about. My point to you was that PCIDs can not be used to to replace or in lieu of TLB shootdowns because they *only* make TLB entries live longer. Their entire purpose is to make things live longer and to reduce the cost of the implicit TLB shootdowns that we do as a part of a context switch. I'm not sure if it will have a benefit overall. It depends on the increase in shootdown cost vs. the decrease in TLB refill cost at context switch. I think someone hacked up some code to do it (maybe just internally to Intel), so if anyone is seriously interested in implementing it, let me know and I'll see if I can dig it up.