Re: Athlon/AGP issue update

[David Woodhouse <dwmw2@infradead.org>]

masp0008@stud.uni-saarland.de said:
>  speculative write operations always set the cache line dirty bit,
> even if the write operations is not executed (e.g. discarded due to a
> mispredicted jump) 

How predictable is this? Dealing with non-coherent memory is perfectly
normal - could we manage to work around this problem by flushing the caches
when the CPU _might_ have dirtied a cache line rather than only when we know
we've actually written to memory? Something like...

--- old.c	Wed Jan 23 11:31:01 2002
+++ new.c	Wed Jan 23 11:30:30 2002
@@ -1,5 +1,7 @@
 
 	if (condition) {
 		writeb();
-		simon_says_flush_cache_page();
 	}
+/* Flush the cache unconditionally - a speculative write may have dirtied
+   the cache line even though it didn't actually happen. */
+		simon_says_flush_cache_page();


Of course, if the behaviour is completely random, and the CPU will dirty
random cache lines from all over the place, even from completely unrelated
code that just happens to have the 'wrong' address in a register that it
doesn't actually end up dereferencing, that can never work.

--
dwmw2