* [PATCH] MIPS64: 48 bit physaddr support in memory maps
@ 2015-05-13 18:55 Leonid Yegoshin
2015-05-13 21:47 ` David Daney
0 siblings, 1 reply; 3+ messages in thread
From: Leonid Yegoshin @ 2015-05-13 18:55 UTC (permalink / raw)
To: linux-mips, linux-kernel, ralf
Originally, it was set to 40bits only but I6400 has 48bits of physaddr.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
---
arch/mips/include/asm/addrspace.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index ba0925c84b75..d54137602ac5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -53,7 +53,7 @@
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
- _CONST64_(0x000000ffffffffff))
+ _CONST64_(0x0000ffffffffffff))
#ifdef CONFIG_64BIT
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] MIPS64: 48 bit physaddr support in memory maps
2015-05-13 18:55 [PATCH] MIPS64: 48 bit physaddr support in memory maps Leonid Yegoshin
@ 2015-05-13 21:47 ` David Daney
2015-05-13 22:58 ` Leonid Yegoshin
0 siblings, 1 reply; 3+ messages in thread
From: David Daney @ 2015-05-13 21:47 UTC (permalink / raw)
To: Leonid Yegoshin; +Cc: linux-mips, linux-kernel, ralf
On 05/13/2015 11:55 AM, Leonid Yegoshin wrote:
> Originally, it was set to 40bits only but I6400 has 48bits of physaddr.
>
Why not go to the architectural limit of 59 bits?
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> ---
> arch/mips/include/asm/addrspace.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
> index ba0925c84b75..d54137602ac5 100644
> --- a/arch/mips/include/asm/addrspace.h
> +++ b/arch/mips/include/asm/addrspace.h
> @@ -53,7 +53,7 @@
> */
> #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
> #define XPHYSADDR(a) ((_ACAST64_(a)) & \
> - _CONST64_(0x000000ffffffffff))
> + _CONST64_(0x0000ffffffffffff))
>
> #ifdef CONFIG_64BIT
>
>
> --
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>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] MIPS64: 48 bit physaddr support in memory maps
2015-05-13 21:47 ` David Daney
@ 2015-05-13 22:58 ` Leonid Yegoshin
0 siblings, 0 replies; 3+ messages in thread
From: Leonid Yegoshin @ 2015-05-13 22:58 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips, linux-kernel, ralf
On 05/13/2015 02:47 PM, David Daney wrote:
> On 05/13/2015 11:55 AM, Leonid Yegoshin wrote:
>> Originally, it was set to 40bits only but I6400 has 48bits of physaddr.
>>
>
> Why not go to the architectural limit of 59 bits?
>
Because any physaddr should fit PTE and EntryLo register and we also
need 5 or 7 SW bits in PTE.
Even with fixed PTE bits layout from
http://patchwork.linux-mips.org/patch/7613/
we need 5 or 7 additional bits, so the real limit is 54. And 54 is
actually specified as a limit in EntryLo starting from MIPS R2.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-05-13 18:55 [PATCH] MIPS64: 48 bit physaddr support in memory maps Leonid Yegoshin
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