From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754716AbbEUAp5 (ORCPT ); Wed, 20 May 2015 20:45:57 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:34072 "EHLO mail-pd0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752819AbbEUApx (ORCPT ); Wed, 20 May 2015 20:45:53 -0400 Message-ID: <555D2AB9.1020903@rock-chips.com> Date: Thu, 21 May 2015 08:45:45 +0800 From: Chris Zhong User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Doug Anderson , Heiko Stuebner CC: linux-rockchip@lists.infradead.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: rockchip: restore dapswjdp after suspend References: <1432154048-19126-1-git-send-email-dianders@chromium.org> In-Reply-To: <1432154048-19126-1-git-send-email-dianders@chromium.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Doug Thank you for pointing out. Reviewed-by: Chris Zhong On 05/21/2015 04:34 AM, Doug Anderson wrote: > In the commit (0ea001d ARM: rockchip: disable dapswjdp during suspend) > we made the assumption that we didn't need to restore dapswjdp after > suspend because "the MASKROM will enable it back". > > It turns out that's not a safe assumption. In some cases (pending > interrupts) it's possible that the WFI might act as a no-op and the > MaskROM will never run. Since we're changing the bit, we should > restore it ourselves. > > Signed-off-by: Doug Anderson > --- > arch/arm/mach-rockchip/pm.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c > index b0dcbe2..a7be465 100644 > --- a/arch/arm/mach-rockchip/pm.c > +++ b/arch/arm/mach-rockchip/pm.c > @@ -48,6 +48,7 @@ static struct regmap *sgrf_regmap; > > static u32 rk3288_pmu_pwr_mode_con; > static u32 rk3288_sgrf_soc_con0; > +static u32 rk3288_sgrf_cpu_con0; > > static inline u32 rk3288_l2_config(void) > { > @@ -70,6 +71,7 @@ static void rk3288_slp_mode_set(int level) > { > u32 mode_set, mode_set1; > > + regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0); > regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); > > regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, > @@ -129,6 +131,9 @@ static void rk3288_slp_mode_set(int level) > > static void rk3288_slp_mode_set_resume(void) > { > + regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, > + rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE); > + > regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, > rk3288_pmu_pwr_mode_con); >