From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754783AbbEUCCz (ORCPT ); Wed, 20 May 2015 22:02:55 -0400 Received: from va-smtp01.263.net ([54.88.144.211]:47632 "EHLO va-smtp01.263.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753640AbbEUCCy (ORCPT ); Wed, 20 May 2015 22:02:54 -0400 X-RL-SENDER: huangtao@rock-chips.com X-FST-TO: huangtao@rock-chips.com X-SENDER-IP: 127.0.0.1 X-LOGIN-NAME: huangtao@rock-chips.com X-UNIQUE-TAG: <6049156cadd2f800546f41f465768fff> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 1 Message-ID: <555D3CB7.2000002@rock-chips.com> Date: Thu, 21 May 2015 10:02:31 +0800 From: "Huang, Tao" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Doug Anderson CC: Heiko Stuebner , linux@arm.linux.org.uk, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org, Tony Xie Subject: Re: [PATCH] ARM: rockchip: restore dapswjdp after suspend References: <1432154048-19126-1-git-send-email-dianders@chromium.org> In-Reply-To: <1432154048-19126-1-git-send-email-dianders@chromium.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Doug: 在 2015年05月21日 04:34, Doug Anderson 写道: > In the commit (0ea001d ARM: rockchip: disable dapswjdp during suspend) > we made the assumption that we didn't need to restore dapswjdp after > suspend because "the MASKROM will enable it back". > > It turns out that's not a safe assumption. In some cases (pending > interrupts) it's possible that the WFI might act as a no-op and the > MaskROM will never run. I don't think this can happen. It seems we set PMU_GLOBAL_INT_DISABLE bit, which means in power off flow, the IRQ will not accepted until the ARM is power off. Do you see the SGRF_CPU_CON0[0] is 0 after resume? Anyway, restore the value is okay, which make the code more symmetrically Since we're changing the bit, we should > restore it ourselves. > > Signed-off-by: Doug Anderson > --- > arch/arm/mach-rockchip/pm.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c > index b0dcbe2..a7be465 100644 > --- a/arch/arm/mach-rockchip/pm.c > +++ b/arch/arm/mach-rockchip/pm.c > @@ -48,6 +48,7 @@ static struct regmap *sgrf_regmap; > > static u32 rk3288_pmu_pwr_mode_con; > static u32 rk3288_sgrf_soc_con0; > +static u32 rk3288_sgrf_cpu_con0; > > static inline u32 rk3288_l2_config(void) > { > @@ -70,6 +71,7 @@ static void rk3288_slp_mode_set(int level) > { > u32 mode_set, mode_set1; > > + regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0); > regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); > > regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, > @@ -129,6 +131,9 @@ static void rk3288_slp_mode_set(int level) > > static void rk3288_slp_mode_set_resume(void) > { > + regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, > + rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE); > + > regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, > rk3288_pmu_pwr_mode_con); > >