From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753115AbbE0QnW (ORCPT ); Wed, 27 May 2015 12:43:22 -0400 Received: from mail-bn1bon0140.outbound.protection.outlook.com ([157.56.111.140]:46544 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753041AbbE0QnP (ORCPT ); Wed, 27 May 2015 12:43:15 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; apm.com; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NP0P3X-08-LKD-02 X-M-MSG: Message-ID: <5565F40C.8010004@amd.com> Date: Wed, 27 May 2015 11:42:52 -0500 From: Suravee Suthikulanit User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Lorenzo Pieralisi , , CC: Ralf Baechle , "James E.J. Bottomley" , Michael Ellerman , Bjorn Helgaas , Richard Henderson , "Benjamin Herrenschmidt" , David Howells , Russell King , Tony Luck , "David S. Miller" , Ingo Molnar , Michal Simek , Koichi Yasutake , Chris Zankel , "Arnd Bergmann" , Krzysztof Halasa , Phil Edworthy , Jason Gunthorpe , Jingoo Han , "Lucas Stach" , Simon Horman , "Minghuan Lian" , Murali Karicheri , Tanmay Inamdar , Kishon Vijay Abraham I , Thierry Reding , Thomas Petazzoni , Will Deacon , Jayachandran C Subject: Re: [RFC/RFT PATCH] PCI: move pci_read_bridge_bases to the generic PCI layer References: <1432214067-2752-1-git-send-email-lorenzo.pieralisi@arm.com> In-Reply-To: <1432214067-2752-1-git-send-email-lorenzo.pieralisi@arm.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1BFFO11FD048;1:QwJRhlmG2DGmPtro4gdIAVuH5z0adhIgIsM/OBjZoxeq+5I2hL+HXRiuuy5OrqRlOV2r/Lho/+aqr2VOccfyRgp0tdwcpleL+bWQ+z42o98NsmxQF6L+VWb8jmK95cXwvt4wk2ShwNjLM9VTI5U5wMp6Il0aYN+c7WDDEBL87dM5JJwrCdqaONb1sZPs/nWEAfdNNwt3+f51NZkQOe88KAvksFkPE2n1/WIPHLV2LL8+e9mJybA43898dmVDkrDN9bVGnh2ay03Jmg/oTU2hEskrPQH9bbG7gAeDYGl/FAHqo3csxcmjVyOro8L6wPxCe/IZZd+KtwYBbbg8r9xGOQ== X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(199003)(24454002)(377454003)(51704005)(189002)(479174004)(164054003)(47776003)(83506001)(189998001)(97736004)(46102003)(65956001)(65806001)(33656002)(64706001)(19580395003)(80316001)(19580405001)(5001770100001)(65816999)(4001540100001)(54356999)(5001860100001)(50986999)(5001830100001)(76176999)(2201001)(101416001)(64126003)(87266999)(86362001)(4001350100001)(87936001)(23746002)(77096005)(36756003)(105586002)(77156002)(106466001)(68736005)(50466002)(92566002)(2950100001)(59896002)(120886001)(62966003)(7059030)(41533002)(2101003);DIR:OUT;SFP:1102;SCL:1;SRVR:CY1PR02MB1119;H:atltwp02.amd.com;FPR:;SPF:None;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR02MB1119; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(520003)(3002001);SRVR:CY1PR02MB1119;BCL:0;PCL:0;RULEID:;SRVR:CY1PR02MB1119; X-Forefront-PRVS: 05891FB07F X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2015 16:43:11.0093 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1119 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lorenzo, Sorry for late reply. On 5/21/2015 8:14 AM, Lorenzo Pieralisi wrote: > When a PCI bus is scanned, upon PCI bridge detection the kernel > has to read the bridge registers to set-up its resources so that > the PCI resource hierarchy can be validated properly. > > Most if not all architectures read PCI bridge registers in the > pcibios_fixup_bus hook, that is called by the PCI generic layer > whenever a PCI bus is scanned. > > Since pci_read_bridge_bases is an arch agnostic operation (and it > is carried out on all architectures) it can be moved to the generic > PCI layer in order to consolidate code and remove the respective > calls from the architectures back-ends. > > The PCI_PROBE_ONLY flag is not checked before calling > pci_read_bridge_buses in the generic layer since reading the bridge > bases is not related to resources assignment; this implies that it > can be carried out safely on PCI_PROBE_ONLY systems too and should > not affect architectures (alpha, mips) that check the PCI_PROBE_ONLY > flag before reading the bridge bases. > > Signed-off-by: Lorenzo Pieralisi > Cc: Ralf Baechle > Cc: James E.J. Bottomley > Cc: Michael Ellerman > Cc: Bjorn Helgaas > Cc: Richard Henderson > Cc: Benjamin Herrenschmidt > Cc: David Howells > Cc: Russell King > Cc: Tony Luck > Cc: David S. Miller > Cc: Ingo Molnar > Cc: Michal Simek > Cc: Koichi Yasutake > Cc: Chris Zankel > --- > arch/alpha/kernel/pci.c | 7 +------ > arch/frv/mb93090-mb00/pci-vdk.c | 2 -- > arch/ia64/pci/pci.c | 1 - > arch/microblaze/pci/pci-common.c | 9 +-------- > arch/mips/pci/pci.c | 6 ------ > arch/mn10300/unit-asb2305/pci.c | 1 - > arch/powerpc/kernel/pci-common.c | 8 +------- > arch/x86/pci/common.c | 1 - > arch/xtensa/kernel/pci.c | 4 ---- > drivers/parisc/dino.c | 3 --- > drivers/parisc/lba_pci.c | 1 - > drivers/pci/probe.c | 11 ++++++++++- > 12 files changed, 13 insertions(+), 41 deletions(-) > > [.....] > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 062fee6..335d9f2 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -453,7 +453,11 @@ void pci_read_bridge_bases(struct pci_bus *child) > struct resource *res; > int i; > > - if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ > + /* > + * If it is not a PCI bridge there is nothing to read > + */ > + if (pci_is_root_bus(child) || !dev || > + !((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)) > return; > > dev_info(&dev->dev, "PCI bridge to %pR%s\n", > @@ -1878,6 +1882,11 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus) > * all PCI-to-PCI bridges on this bus. > */ > if (!bus->is_added) { > + /* > + * Read and initialize bridge resources. > + */ > + pci_read_bridge_bases(bus); > + > dev_dbg(&bus->dev, "fixups for bus\n"); > pcibios_fixup_bus(bus); > bus->is_added = 1; > So, I have tested the patch on ARM64 system w/ PROBE_ONLY mode, and noticed that we are calling pci_read_bridge_bases() after adding the devices on the slots. This is not soon enough since the downstream devices still failing to claim resources. However, do you think we can move pci_read_bridge_bases() before the pci_scan_slot() loop? Thanks, Suravee