From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932075AbbE0S6c (ORCPT ); Wed, 27 May 2015 14:58:32 -0400 Received: from mail-bn1bbn0101.outbound.protection.outlook.com ([157.56.111.101]:50461 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751701AbbE0S63 (ORCPT ); Wed, 27 May 2015 14:58:29 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=yorksun@freescale.com; Message-ID: <556613CE.8020906@freescale.com> Date: Wed, 27 May 2015 11:58:22 -0700 From: York Sun User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Guenter Roeck CC: Michael Turquette , , , , , , Subject: Re: clock driver References: <5564C58B.9050400@freescale.com> <20150526223829.GA26454@roeck-us.net> <55650DBA.5000304@freescale.com> <5565108D.2020502@freescale.com> <20150527173055.22384.74368@quantum> <556602BC.6040203@freescale.com> <20150527181521.GA19448@roeck-us.net> <55660BF2.6000002@freescale.com> <20150527185442.GA6607@roeck-us.net> In-Reply-To: <20150527185442.GA6607@roeck-us.net> Content-Type: text/plain; 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X-Microsoft-Exchange-Diagnostics: =?Windows-1252?Q?1;BLUPR03MB151;9:q7APzFQMqtx7MzNi+9ORthUr1zT0B1vmAxJ1C53?= =?Windows-1252?Q?z3Z+YrmWzzgyS4Fw/98P10t2cdoUDLciXWgrzdklWZAV8xhS21my8maQ?= =?Windows-1252?Q?Bur5wEVofrKS27ErrNQzLCcI2svngBhBZ9qmFEs1NuGIC/+YY7iWxLqk?= =?Windows-1252?Q?MnOKcjIyXUeqQUwlbvJ0j3tEnVRcBbWTkaFC6W7LZL0e+tEMul8guph9?= =?Windows-1252?Q?1LYy+DG5VZusiFxsEc+iaCUARflkKvqERAfzXIZTuJh0TbIIwwtlLfdX?= =?Windows-1252?Q?YoeDM2+yG1s6wOK634Ql8i86GjVR9gvfoFVeaH1aPPiRZraL4+xRMZCs?= =?Windows-1252?Q?OQ5aXhabgDlyy2LZXAuHc4n+SJz4jtPN9iRQdWSfv8UIJlAR6532GII9?= =?Windows-1252?Q?AjE7xETjhd64s9w7uCAI9kRUVpQMec5uffzmabFaRGKEDox0wzD+Ojai?= =?Windows-1252?Q?at0AGZ55CK7xRtqdCa+G5T1yCzACq79D34OcGrf2uoKhQYg1tq9GsqNy?= =?Windows-1252?Q?6qV/cPn3UJoMYHdc+kMdM5K4P/Eb/Uds1xCXxwV8rmyafX7kcZJ9bw9Y?= =?Windows-1252?Q?Kgycn7K4k+dqUQ9sLGBSsctqn6Pfjv/zlaDNLYJZnFF28gzxKMPxozmn?= =?Windows-1252?Q?xvExoq7aF08SNd6nbHMZ36gSkKJJ6LYG26dxZbgLoF8vt51cijwOPX7O?= =?Windows-1252?Q?RX/u8EQee4wMBI+x0XY5tiVhwVF/BjNqpUOwLQlMTYAbRBSTK3Y/YyXu?= =?Windows-1252?Q?LkbmJOlgpzNSJzU+VGl8fQb4VbbBJo7FXvXfaTZT+OYac2HubgAHPYnZ?= =?Windows-1252?Q?YN6hpA6uO3ZiVrvuC+iuNpYVNAObxcBO/IMg80ajqcm2TvhHGp4TYPoc?= =?Windows-1252?Q?fjtFUzJtP032VSl+AEVMWH4+IqLjFyJzBmYJFThI3uJsAd6BVEYrqzjc?= =?Windows-1252?Q?VFg+Y/olqcPnbrpab6QyJ7zaF0WaeXopaxZoQyy+x38WhDpU3sF5fZAo?= =?Windows-1252?Q?Y42JaakGniErkF+c6XV2AdVD9keK9eNZ49h2kaS2u3D+qLlw36xKh4FB?= =?Windows-1252?Q?rSRxhg1L4KJk5toiIW231vM0CId2CQbhf7GH4O5ZThZNMpsXZPSJ1/Ku?= =?Windows-1252?Q?shEv83iSeU4tPIjMaIVM6Goj3vWFhcasKpDWdtC3RxwmWB7uEoddNlbw?= =?Windows-1252?Q?MT09bqYsBPiAMArhNu8Do+Vg80Hv7Jcm1wwEA9HD0NMAs7mu8q7XIlCG?= =?Windows-1252?Q?Tfrfxwb6WwdS02/bZIzKjMZpfWyyKxG+atWtMQedXHLpYEJrG5PdME2Q?= =?Windows-1252?Q?jasu0Mnh7nOKDFKbyveRBpiapo11u+HV2NDT1ODaV1X1CQP6AfVCu9wi?= =?Windows-1252?Q?MKkJJMFAdDpV+gjEveRdlAqIziFq1+tlrlrQBDO9WQTqQFJt9VzXg/Nx?= =?Windows-1252?Q?PGYQiO1UW0yn4f6PX0exEArl9Hf6omw+oHGVMDvzIQ8dstpJoT8cs6SK?= =?Windows-1252?Q?KgJvxG08MUUWR9la0SjixhzwvTmgYPPHUtZ4L/mjUoR42cSye9/mV7th?= =?Windows-1252?Q?2YyJJEqD8db0td3wPRoRCofOAyNz4FXxxFQVigjN2TxDDcN1KdmMuCw?= =?Windows-1252?Q?=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1;BLUPR03MB151;3:8Wk8KG/2Ua1G/E0uf6renbRjDdcRuwOTeCogqs4UeAOxyI6pdbY9N9JFX/Tnwq+oaGzhgIjfeseAsauHXhNU75FgIcGfWgEN14/DanNFFnRn2XV7r848auZO8wKq+evPwp3tH4Pf9y8tm89VfS2Icg==;10:L8CLITPoM/UBhPbC30mbI3E6autURTaMPLckwPqc9yaQkly8WqtexI5jF2kUuw+eLDLifpAnLzoXHnhOBu173d8l3+T9Y6513NaMjdYCPr0=;6:6mN5bdr3S0b2mEY9WqxsjatkmcteS38bFXnJWTZmE4zkp50k63vfOOIXWg4zpknw X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2015 18:58:26.6168 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB151 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/27/2015 11:54 AM, Guenter Roeck wrote: > On Wed, May 27, 2015 at 11:24:50AM -0700, York Sun wrote: >> >>> >>> Someone suggested earlier that the clocks should be set from the PCIe driver. >>> Question here is really if you need to control the clocks from user space. >>> Even if you do, the driver for the chip _using_ the clocks would be better >>> suited for changing the clock rates than the clock driver itself. This way it >>> can ensure that the clock rates are sane for the given use case, and the use >>> case is kept out of the clock driver. >>> >>>> I wrote a driver for the PCIe card to load FPGA images. To setup the clocks, I >>>> rewrote the SI5338 driver and set the desired frequencies using sysfs. This >>>> driver has a feature to import/dump the raw configuration data. That's one >>>> feature I plan to use, at least for debugging. >>>> >>> With the above in mind, the idea would be for the PCIe driver to set the clock >>> rates. >> >> I am interested in this path. Can you explain a little bit more about setting >> the clock rates? I have no experience on CCF. >> > The API functions are documented in include/linux/clk.h. What you are looking > for here would be clk_set_rate() and related functions such as clk_round_rate(), > and of course support functions such as devm_clk_get(), clk_prepare_enable(), > and clk_disable_unprepare(). > > You can find lots of examples on how this works if you search for clk_set_rate() > in the kernel source. Yes I saw them. I have no experience with CCF. It will take some learning time. I am trying to find an SI5xx EVB board so I can try it out. > >>> >>>> I don't think device tree is the best for my application because I will have >>>> about 30 clock chips to program in the complete system. It is easier to use user >>>> space application to do so from I2C bus. >>>> >>> Devicetree is static, so you might have to use devicetree overlays if the >>> programming changes at runtime. Not sure why the number of clock chips >>> would make that non-feasible, though. >> >> I mean the existence is unknown for many chips. The baseline is I can't use >> static data. >> >>> >>> On a side note, we are using devicetree a lot for PCIe devices. >> >> It's tempting. I want to explore this direction at a later phase of my project. >> I will appreciate if you can point me to something. >> > I can send you some devicetree files if you think that would help. Note that we > are heavily using devicetree overlays, so this is all a bit WIP. Yes, please send them to me. > >>> >>>> Earlier Guenter helped me to comb through the idea and we concluded CCF may not >>>> be the best fit for this application. I wonder if CCF is the only way to get >>> >>> Well, you did ;-). I think it would be feasible, but you would have to change >>> your viewpoint (in respect to how to control the clocks). >> >> Right, I did. I will revisit this after bring up the platform initially, when I >> have more knowledge about those clocks. Maybe I should add an interface for my >> FPGA driver to request clock rates, instead of setting them from clock driver. >> It sounds better. >> > Yes, that would be the idea. Essentially your FPGA driver could either determine > the clock rate(s) it needs internally, or you could set the clock rate(s) > through sysfs attributes attached to the FPGA driver. The FPGA driver would then > use clk_set_rate() to set the rate in the clock chip. > Sounds promising. Thanks for the guidance. York