From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932106AbbE1IUu (ORCPT ); Thu, 28 May 2015 04:20:50 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:32717 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753395AbbE1IUg (ORCPT ); Thu, 28 May 2015 04:20:36 -0400 Message-ID: <5566CF13.8060806@huawei.com> Date: Thu, 28 May 2015 16:17:23 +0800 From: Bintian User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 To: Michael Turquette , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , Subject: Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC References: <1432440671-25235-1-git-send-email-bintian.wang@huawei.com> <1432440671-25235-3-git-send-email-bintian.wang@huawei.com> <20150528052608.22384.96747@quantum> In-Reply-To: <20150528052608.22384.96747@quantum> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.111.68.103] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.5566CF32.0005,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 87fed66981d49fc0c269df6a297fc04b Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Mike, On 2015/5/28 13:26, Michael Turquette wrote: > Quoting Bintian Wang (2015-05-23 21:11:11) >> Add clock drivers for hi6220 SoC, this driver controls the SoC >> registers to supply different clocks to different IPs in the SoC. >> >> We add one divider clock for hi6220 because the divider in hi6220 >> also has a mask bit but it doesnot obey the rule defined by flag >> "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by >> left shift fixed bits (e.g. 16 bits), so we add this divider clock >> to handle it. >> >> Signed-off-by: Jorge Ramirez-Ortiz >> Signed-off-by: Bintian Wang >> Acked-by: Haojian Zhuang >> Reviewed-by: Zhangfei Gao >> Tested-by: Will Deacon >> Tested-by: Tyler Baker > > Hi Bintian, > > Thanks for making the changes requested by Stephen. I've taken his patch > to add assigned-clock-rate/parent support for AMBA interconnects and > applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top > of that. You can find it at: > > git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 Thank you very much! I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock", which described the dt binding of clk, and it is also acked by Stephen(v4 is the same to v5). > I have merged this into clk-next so it can get some cycles in > linux-next. > > Stephen, > > Can you send your patch out to Russell properly? It needs his ack (or > for him to take it outright) in order to unblock the hi6220 clock driver > from being merged. It doesn't block hi6220 clock driver now, because the UART1 is not enabled in hi6220 dts now. Thanks! Bintian > > Regards, > Mike > > . >