From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422644AbbE2S2N (ORCPT ); Fri, 29 May 2015 14:28:13 -0400 Received: from mail-bl2on0123.outbound.protection.outlook.com ([65.55.169.123]:60976 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1161065AbbE2S2B (ORCPT ); Fri, 29 May 2015 14:28:01 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NP4JAE-08-4NX-02 X-M-MSG: Message-ID: <5568AFA4.4040101@amd.com> Date: Fri, 29 May 2015 13:27:48 -0500 From: Aravind Gopalakrishnan User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Borislav Petkov CC: , , , Subject: Re: [PATCH 4/6] edac, mce_amd_inj: Add capability to trigger apic interrupts References: <1432753418-2985-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <1432753418-2985-5-git-send-email-Aravind.Gopalakrishnan@amd.com> <20150529153657.GH31435@pd.tnic> In-Reply-To: <20150529153657.GH31435@pd.tnic> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.180.168.240] X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BY2FFO11FD048;1:TyIitJYhqUSpUX+enCJQAwot7IwrWTM0AZa3WrHFaGzmwadpPyEB7tDgJgAIQmN1rlCT4I3TWLXHjffyP3Fr7icthEfL5wHt16VlhlCmWzPbex//hEzd1vKrFTwMi09frmP+7OwdvgRGzWWZph9MM9HT0TNGOSoF+nIsKbEHqfcEc3+P0PaJEDR6+YEsKiV/8K6ztIKfyiZ7Rz9R9bmcptCzSIjirGq8Np45x4Wp1hq14cLil7Cz2XqNljgp7kJ3A/7JWb/Jl8iN8liwvrlAVw== X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(51704005)(479174004)(189002)(199003)(24454002)(164054003)(377454003)(87266999)(23676002)(80316001)(120886001)(54356999)(65816999)(64126003)(83506001)(86362001)(106466001)(50986999)(36756003)(76176999)(50466002)(77156002)(62966003)(97736004)(4001540100001)(4001350100001)(5001860100001)(5001830100001)(87936001)(59896002)(5001920100001)(189998001)(65806001)(64706001)(33656002)(46102003)(47776003)(92566002)(68736005)(2950100001)(77096005)(101416001)(110136002)(65956001)(105586002);DIR:OUT;SFP:1102;SCL:1;SRVR:BY1PR02MB1116;H:atltwp02.amd.com;FPR:;SPF:None;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1116; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(520003)(5005006)(3002001);SRVR:BY1PR02MB1116;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1116; X-Forefront-PRVS: 059185FE08 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2015 18:27:55.6648 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR02MB1116 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/29/2015 10:36 AM, Borislav Petkov wrote: > On Wed, May 27, 2015 at 02:03:36PM -0500, Aravind Gopalakrishnan wrote: >> >> +static void trigger_dfr_int(void *info) >> +{ >> + asm volatile("int $244"); >> +} >> + >> +static void trigger_thr_int(void *info) >> +{ >> + asm volatile("int $249"); >> +} > Hardcoded naked numbers huh? > > Guess what happens when someone changes DEFERRED_ERROR_VECTOR and > THRESHOLD_APIC_VECTOR. Right. Sorry about that. Fixed it thusly: u8 dfr_vec = DEFERRED_ERROR_VECTOR; asm volatile("int %0" :: "n" (dfr_vec)); and similar for threshold interrupt as well. Tested the above and it seems to work fine. > > - smp_call_function_single(cpu, trigger_mce, NULL, 0); > + if (inj_type == DFR_INT_INJ) > + smp_call_function_single(cpu, trigger_dfr_int, NULL, 0); > + else if (inj_type == THR_INT_INJ) > + smp_call_function_single(cpu, trigger_thr_int, NULL, 0); > + else > + smp_call_function_single(cpu, trigger_mce, NULL, 0); > I guess a switch-case is kinda offering itself here... > Ok, will switch it:) Thanks, -Aravind.