From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753169AbbFGCwH (ORCPT ); Sat, 6 Jun 2015 22:52:07 -0400 Received: from regular1.263xmail.com ([211.150.99.133]:57807 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753101AbbFGCwE (ORCPT ); Sat, 6 Jun 2015 22:52:04 -0400 X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED: 0 X-RL-SENDER: wxt@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 220.250.50.109 X-LOGIN-NAME: wxt@rock-chips.com X-UNIQUE-TAG: <82ae7ac0134a396a701ac2ddc297fde9> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <5573B1CA.1050204@rock-chips.com> Date: Sun, 07 Jun 2015 10:51:54 +0800 From: Caesar Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Doug Anderson CC: Heiko Stuebner , Dmitry Torokhov , "open list:ARM/Rockchip SoC..." , Russell King , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v4 1/3] ARM: rockchip: fix the CPU soft reset References: <1433523923-4755-1-git-send-email-wxt@rock-chips.com> <1433523923-4755-2-git-send-email-wxt@rock-chips.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2015年06月06日 04:55, Doug Anderson 写道: > Caesar, > > On Fri, Jun 5, 2015 at 10:05 AM, Caesar Wang wrote: >> + if (!on) >> + reset_control_assert(rstc); >> + >> + ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); >> + if (ret < 0) { >> + pr_err("%s: could not update power domain\n", __func__); >> + reset_control_put(rstc); >> + return ret; >> + } >> + >> if (on) >> reset_control_deassert(rstc); >> - else >> - reset_control_assert(rstc); > As Heiko indicated in the previous patchset, he thought it would be > nice to move the 'pmu_power_domain_is_on(pd)' to before you deasserted > reset. ...but then I pointed out that you tested that in patch set #2 > and it didn't work. > > Talking to Heiko offline he thought that perhaps you could make > 'pmu_power_domain_is_on(pd)' work if you increased your 'udelay(10);' > in rockchip_boot_secondary(). Perhaps the old > 'pmu_power_domain_is_on' was acting like an extra bit of delay and > that's why moving it broke things. > > > I actually went back and tested patch set #2 and it worked for me, so > I couldn't test Heiko's theory. Could you go and reproduce the > problem with patch set #2 again and then try increasing the udelay() > and see if your problems go away? If that works, it might be a > slightly better solution. Note that I think Heiko had a slightly > cleaner version of your patch set #2 that he posted in response to > your patch set #3. @@ -150,13 +159,15 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc * */ - udelay(10); + udelay(20); I increased the 'udelay(20)' or 'udelay(50)' in rockchip_boot_secondary(). Set#2 also can repro this issue over 22600 cycles with testing scripts. (about 1 hours) log: ================= 226 ============ [ 4069.134419] CPU1: shutdown [ 4069.164431] CPU2: shutdown [ 4069.204475] CPU3: shutdown ...... [ 4072.454453] CPU1: shutdown [ 4072.504436] CPU2: shutdown [ 4072.554426] CPU3: shutdown [ 4072.577827] CPU1: Booted secondary processor [ 4072.582611] CPU2: Booted secondary processor [ 4072.587426] CPU3: Booted secondary processor The set #4 will be better work. > > -Doug > > > -- Thanks, - Caesar