From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751530AbbFGFwE (ORCPT ); Sun, 7 Jun 2015 01:52:04 -0400 Received: from regular1.263xmail.com ([211.150.99.132]:55589 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750920AbbFGFvy (ORCPT ); Sun, 7 Jun 2015 01:51:54 -0400 X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED: 0 X-RL-SENDER: wxt@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 103.47.144.135 X-LOGIN-NAME: wxt@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <5573DBDC.2010204@rock-chips.com> Date: Sun, 07 Jun 2015 13:51:24 +0800 From: Caesar Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Doug Anderson CC: Heiko Stuebner , Dmitry Torokhov , "open list:ARM/Rockchip SoC..." , Russell King , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v4 1/3] ARM: rockchip: fix the CPU soft reset References: <1433523923-4755-1-git-send-email-wxt@rock-chips.com> <1433523923-4755-2-git-send-email-wxt@rock-chips.com> <5573B1CA.1050204@rock-chips.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2015年06月07日 11:43, Doug Anderson 写道: > Caesar, > > On Sat, Jun 6, 2015 at 7:51 PM, Caesar Wang wrote: >> @@ -150,13 +159,15 @@ static int __cpuinit rockchip_boot_secondary(unsigned >> int cpu, >> * sram_base_addr + 4: 0xdeadbeaf >> * sram_base_addr + 8: start address for pc >> * */ >> - udelay(10); >> + udelay(20); >> >> I increased the 'udelay(20)' or 'udelay(50)' in rockchip_boot_secondary(). >> Set#2 also can repro this issue over 22600 cycles with testing scripts. >> (about 1 hours) >> >> log: >> ================= 226 ============ >> [ 4069.134419] CPU1: shutdown >> [ 4069.164431] CPU2: shutdown >> [ 4069.204475] CPU3: shutdown >> ...... >> [ 4072.454453] CPU1: shutdown >> [ 4072.504436] CPU2: shutdown >> [ 4072.554426] CPU3: shutdown >> [ 4072.577827] CPU1: Booted secondary processor >> [ 4072.582611] CPU2: Booted secondary processor >> [ 4072.587426] CPU3: Booted secondary processor >> >> >> The set #4 will be better work. > OK, I'm OK with this, but I'd like to get Heiko's opinion. > > Also: > * Just for kicks, does mdelay(1) work? I know that's 100x more than OK, it should delay more time. the mdelay(1) can be work over 50000 cycles, so that should be work. Perhaps, can we use 'usleep_range(500, 1000)' to work. Heiko, do you agree with it? > udelay(10), but previously we were actually looping waiting for the > power domain, right? ...so maybe the old code used to introduce a > pretty big delay. > > * Does anyone from the chip design team have any idea why patch set #4 > works but patch set #2 doesn't? I know it's Sunday morning in China > right now, but maybe you could ask Monday? > > > Thanks! > > -Doug > > > -- Thanks, - Caesar