Re: [uClinux-dev] m68k compile issue with 4.0.5

[Greg Ungerer <gerg@uclinux.org>]

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Hi Waldemar,

On 17/06/15 15:42, Waldemar Brodkorb wrote:
> Hi Greg,
> Greg Ungerer wrote,
>> I don't have any compile (or runtime) problems with m5208evb_defconfig
>> on linux-4.0.5 either. That is close to what most people use with qemu.
>> What .config are you using?
> Are you sure the defconfig creates a bootable image?
>
> I still need at least two patches.
>
> http://cgit.openadk.org/cgi/cgit/openadk.git/tree/target/m68k/qemu-m68k/patches/4.0.5/qemu-coldfire.patch
> Without this one I get black screen.
>
> http://cgit.openadk.org/cgi/cgit/openadk.git/tree/target/m68k/qemu-m68k/patches/4.0.5/m68k-coldfire-fec.patch
> Without this one I get
> qemu: hardware error: mcf_fec_read: Bad address 0x1c4
> ...
> Abort
>
> Networking still does not work for me after booting with the two
> patches applied:
> fec fec.0 (unnamed net_device) (uninitialized): MDIO read timeout
> fec: probe of fec.0 failed with error -5
>
> Any idea?

The qemu fec driver does not emulate any type of attached phy
or properly support the mdio read/write register.

The attached patch to qemu implements really simple phy support.
Was enough for me to get linux probing and finding a phy.

Regards
Greg


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>From 0a949818b081261b8322da0bef4af92f0e379655 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Thu, 18 Jun 2015 23:27:13 +1000
Subject: [PATCH] m68k: add simple phy support to fec driver

The Linux fec driver needs at least basic PHY support to probe and work.

This code adds a very simple set of register results for a fixed PHY
setup - very similar to that used on an m5208evb board.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 hw/net/mcf_fec.c | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/hw/net/mcf_fec.c b/hw/net/mcf_fec.c
index 4bff3de..2df062f 100644
--- a/hw/net/mcf_fec.c
+++ b/hw/net/mcf_fec.c
@@ -216,6 +216,33 @@ static void mcf_fec_reset(mcf_fec_state *s)
     s->rfsr = 0x500;
 }
 
+#define MMFR_WRITE_OP	(1 << 28)
+#define MMFR_READ_OP	(2 << 28)
+#define MMFR_PHYADDR(v)	(((v) >> 23) & 0x1f)
+#define MMFR_REGNUM(v)	(((v) >> 18) & 0x1f)
+
+static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
+{
+	uint64_t v;
+
+	if (s->mmfr & MMFR_WRITE_OP)
+		return s->mmfr;
+	if (MMFR_PHYADDR(s->mmfr) != 1)
+		return s->mmfr |= 0xffff;
+
+	switch (MMFR_REGNUM(s->mmfr)) {
+	case 0x00: v = 0x3100; break;
+	case 0x01: v = 0x786d; break;
+	case 0x02: v = 0x2000; break;
+	case 0x03: v = 0x5c90; break;
+	case 0x04: v = 0x01e1; break;
+	case 0x05: v = 0xc1e1; break;
+	default: v = 0xffff ; break;
+	}
+	s->mmfr = (s->mmfr & ~0xffff) | v;
+	return s->mmfr;
+}
+
 static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
                              unsigned size)
 {
@@ -226,7 +253,7 @@ static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
     case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
     case 0x014: return 0; /* TDAR */
     case 0x024: return s->ecr;
-    case 0x040: return s->mmfr;
+    case 0x040: return mcf_fec_read_mdio(s);
     case 0x044: return s->mscr;
     case 0x064: return 0; /* MIBC */
     case 0x084: return s->rcr;
@@ -287,8 +314,8 @@ static void mcf_fec_write(void *opaque, hwaddr addr,
         }
         break;
     case 0x040:
-        /* TODO: Implement MII.  */
         s->mmfr = value;
+	s->eir |= FEC_INT_MII;
         break;
     case 0x044:
         s->mscr = value & 0xfe;
-- 
1.9.1