From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75B32314A90 for ; Thu, 9 Apr 2026 19:40:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775763603; cv=none; b=Wxhujizn0nwGBhfCLkkK0G1/bxgezX4ETpsDHHIdVtYAujH+XQkD6s54D6W1HAlL0hQlkVDqe48iMtFFBuKBzjWFqkDq5LNFYsdXol2kOKoexs9619qI7C5jO2oOye8FefvBg45FGZMdEmYztyfGFWDec6JKOS+G+8dNt0650zA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775763603; c=relaxed/simple; bh=wMAXn7AHz1Pnyb5wfz6PvHassX4Bv29DGHx9U06eUDk=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=ABbj3iZ1+ts5vzGH2xNvy/UuVT8kcRZc5g2IdDaqrvBXoh+dIDc7CTlci+NC1QeGSUId6DZzxOZh2n/jiGcWLjP2PzBdNsTVapkPhProrl+j8fZqB8V4BQc95bPx8cZHivmbGi4wrThOfcJUCw9MvYZB6pmlqeY3EF9WCC+caWY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=e3ovq7BA; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="e3ovq7BA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775763602; x=1807299602; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=wMAXn7AHz1Pnyb5wfz6PvHassX4Bv29DGHx9U06eUDk=; b=e3ovq7BAaVnGxl2sW8IVWHADHVvsprCt3Z2Es7vF3QAuEPUu9xjOA9E1 CpMun6hjsuOr+HbISdXpEk88Ke8xQMcunh7yOKmkJTEzDaJvvr6MKDfBn pAcT6HS+fjwipICtuoKhf2OKEWeAyvR3TfYijH/Zvz7dDpbiu+sPC2Evl vjysw83uMf01b8aMxnBcjd1FbA9gg4LJEH2q+wM+SNVVDV+d0PhBXmo7i 1XE4hVkvsM5ADHtsre0kUUalbau+uD889PjZuMrNUfUnSEpUMmO4b2yPc 3/l/mGd9gXsBX0scYxg4Dkk5PoqPflgWDyktjhR3YjplSVUFZ1OwiEXxk g==; X-CSE-ConnectionGUID: sBi7lbkPTJqVbnrWhs51/w== X-CSE-MsgGUID: 6BxX4oepRSuEeGroQigucQ== X-IronPort-AV: E=McAfee;i="6800,10657,11754"; a="80669095" X-IronPort-AV: E=Sophos;i="6.23,170,1770624000"; d="scan'208";a="80669095" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2026 12:40:01 -0700 X-CSE-ConnectionGUID: V6fGeSc2Qu6V3IepytUvPQ== X-CSE-MsgGUID: QvdNC+EtSsW0wI20MmDG1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,170,1770624000"; d="scan'208";a="259335354" Received: from unknown (HELO [10.241.243.39]) ([10.241.243.39]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2026 12:40:00 -0700 Message-ID: <55905b3624a2e36c3af3dc919909e2f199cd00fb.camel@linux.intel.com> Subject: Re: [Patch v4 18/22] sched/cache: Enable cache aware scheduling for multi LLCs NUMA node From: Tim Chen To: Peter Zijlstra Cc: Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Date: Thu, 09 Apr 2026 12:39:59 -0700 In-Reply-To: <20260409133754.GD3126523@noisy.programming.kicks-ass.net> References: <71972e12ab4f08aff422b31e34df09bdbd94de84.1775065312.git.tim.c.chen@linux.intel.com> <20260409133754.GD3126523@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2026-04-09 at 15:37 +0200, Peter Zijlstra wrote: > On Wed, Apr 01, 2026 at 02:52:30PM -0700, Tim Chen wrote: >=20 > > diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c > > index 995a42cb4697..0b1fc1b0709d 100644 > > --- a/kernel/sched/topology.c > > +++ b/kernel/sched/topology.c > > @@ -809,6 +809,7 @@ enum s_alloc { > > }; > > =20 > > #ifdef CONFIG_SCHED_CACHE > > +DEFINE_STATIC_KEY_FALSE(sched_cache_present); > > static bool alloc_sd_llc(const struct cpumask *cpu_map, > > struct s_data *d) > > { > > @@ -2674,6 +2675,7 @@ static int > > build_sched_domains(const struct cpumask *cpu_map, struct sched_domain= _attr *attr) > > { > > enum s_alloc alloc_state =3D sa_none; > > + bool has_multi_llcs =3D false; > > struct sched_domain *sd; > > struct s_data d; > > struct rq *rq =3D NULL; > > @@ -2784,10 +2786,12 @@ build_sched_domains(const struct cpumask *cpu_m= ap, struct sched_domain_attr *att > > * between LLCs and memory channels. > > */ > > nr_llcs =3D sd->span_weight / child->span_weight; > > - if (nr_llcs =3D=3D 1) > > + if (nr_llcs =3D=3D 1) { > > imb =3D sd->span_weight >> 3; > > - else > > + } else { > > imb =3D nr_llcs; > > + has_multi_llcs =3D true; > > + } > > imb =3D max(1U, imb); > > sd->imb_numa_nr =3D imb; > > =20 >=20 > Well that all don't apply :/ >=20 > Also, this seems sub-optimal, we can have multi-llc without NUMA. >=20 > Doesn't the LLC domain having a parent more or less imply there being > multiple and we should be doing this, irrespective of having NUMA? If we have NUMA and single LLC, original thought was that NUMA balancing would be taking care of moving the tasks to preferred node. And that's why we thought it is not necessary to enable cache aware scheduling for that case. Yes, if there's no NUMA and we have a parent group for LLCs, agree that we should enable it. Tim