[PATCH v4 0/6] clk: replace div_mask() by GENMASK()

[PATCH v4 0/6] clk: replace div_mask() by GENMASK()

[Andy Shevchenko]

This series replaces div_mask() macros in many clock providers by GENMASK()
generic helper.

Since there are a lot of patterns like GENMASK(n - 1, 0) I have locally, means
not part of the series, a patch to add GENMASK0(n) and GENMASK0_ULL(n) as
equalent to the longer code line. It's still discussible if we need that one
(not only CLK framework uses such idiom).

Changelog v4:
 - use GENMASK() instead of div_mask() by Stephen Boyd's comment

Changelog v3:
 - fix clk_div_mask() prototype: seems tired like on Friday evening!

Changelog v2:
 - fix patches 5,6,7 where parameter of the macro was d instead of d->width

Andy Shevchenko (6):
  clk: divider: switch to GENMASK()
  clk: mmp: switch to GENMASK()
  clk: socfpga: switch to GENMASK()
  clk: ti: divider: switch to GENMASK()
  clk: tegra: switch to GENMASK()
  ARM: imx: switch to GENMASK()

 arch/arm/mach-imx/clk-fixup-div.c |  7 +++----
 drivers/clk/clk-divider.c         | 18 ++++++++----------
 drivers/clk/mmp/clk-mix.c         |  2 +-
 drivers/clk/socfpga/clk-gate.c    |  2 +-
 drivers/clk/socfpga/clk-periph.c  |  2 +-
 drivers/clk/socfpga/clk.h         |  1 -
 drivers/clk/tegra/clk-divider.c   |  7 +++----
 drivers/clk/ti/divider.c          | 18 ++++++++----------
 8 files changed, 25 insertions(+), 32 deletions(-)

-- 
2.1.4

[PATCH v4 1/6] clk: divider: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/clk-divider.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 25006a8..b9c447f 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -30,8 +30,6 @@
 
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
-#define div_mask(width)	((1 << (width)) - 1)
-
 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
 {
 	unsigned int maxdiv = 0;
@@ -58,12 +56,12 @@ static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
 				unsigned long flags)
 {
 	if (flags & CLK_DIVIDER_ONE_BASED)
-		return div_mask(width);
+		return GENMASK(width - 1, 0);
 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
-		return 1 << div_mask(width);
+		return GENMASK(width - 1, 0);
 	if (table)
 		return _get_table_maxdiv(table);
-	return div_mask(width) + 1;
+	return BIT(width);
 }
 
 static unsigned int _get_table_div(const struct clk_div_table *table,
@@ -138,7 +136,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 	unsigned int val;
 
 	val = clk_readl(divider->reg) >> divider->shift;
-	val &= div_mask(divider->width);
+	val &= GENMASK(divider->width - 1, 0);
 
 	return divider_recalc_rate(hw, parent_rate, val, divider->table,
 				   divider->flags);
@@ -350,7 +348,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
 	/* if read only, just return current value */
 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
 		bestdiv = readl(divider->reg) >> divider->shift;
-		bestdiv &= div_mask(divider->width);
+		bestdiv &= GENMASK(divider->width - 1, 0);
 		bestdiv = _get_div(divider->table, bestdiv, divider->flags);
 		return DIV_ROUND_UP(*prate, bestdiv);
 	}
@@ -372,7 +370,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
 
 	value = _get_val(table, div, flags);
 
-	return min_t(unsigned int, value, div_mask(width));
+	return min_t(unsigned int, value, GENMASK(width - 1, 0));
 }
 EXPORT_SYMBOL_GPL(divider_get_val);
 
@@ -391,10 +389,10 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 		spin_lock_irqsave(divider->lock, flags);
 
 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
-		val = div_mask(divider->width) << (divider->shift + 16);
+		val = GENMASK(divider->width - 1, 0) << (divider->shift + 16);
 	} else {
 		val = clk_readl(divider->reg);
-		val &= ~(div_mask(divider->width) << divider->shift);
+		val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);
 	}
 	val |= value << divider->shift;
 	clk_writel(val, divider->reg);
-- 
2.1.4

[PATCH v4 2/6] clk: mmp: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of custom approach.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/mmp/clk-mix.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
index de6a873..3aad9c8 100644
--- a/drivers/clk/mmp/clk-mix.c
+++ b/drivers/clk/mmp/clk-mix.c
@@ -26,7 +26,7 @@
 
 static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
 {
-	unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
+	unsigned int div_mask = GENMASK(mix->reg_info.width_div - 1, 0);
 	unsigned int maxdiv = 0;
 	struct clk_div_table *clkt;
 
-- 
2.1.4

[PATCH v4 3/6] clk: socfpga: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/socfpga/clk-gate.c   | 2 +-
 drivers/clk/socfpga/clk-periph.c | 2 +-
 drivers/clk/socfpga/clk.h        | 1 -
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index dd3a78c..d61052e 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -110,7 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
 		div = socfpgaclk->fixed_div;
 	else if (socfpgaclk->div_reg) {
 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-		val &= div_mask(socfpgaclk->width);
+		val &= GENMASK(socfpgaclk->width - 1, 0);
 		/* Check for GPIO_DB_CLK by its offset */
 		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
 			div = val + 1;
diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 46531c3..fc410a4 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -36,7 +36,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
 	} else {
 		if (socfpgaclk->div_reg) {
 			val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-			val &= div_mask(socfpgaclk->width);
+			val &= GENMASK(socfpgaclk->width - 1, 0);
 			parent_rate /= (val + 1);
 		}
 		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d291f60..5278156 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -27,7 +27,6 @@
 #define CLKMGR_PERPLL_SRC	0xAC
 
 #define SOCFPGA_MAX_PARENTS		3
-#define div_mask(width) ((1 << (width)) - 1)
 
 extern void __iomem *clk_mgr_base_addr;
 
-- 
2.1.4

[PATCH v4 4/6] clk: ti: divider: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/ti/divider.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index ff5f117..dfe485e 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -28,8 +28,6 @@
 
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
-#define div_mask(d)	((1 << ((d)->width)) - 1)
-
 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
 {
 	unsigned int maxdiv = 0;
@@ -44,12 +42,12 @@ static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
 static unsigned int _get_maxdiv(struct clk_divider *divider)
 {
 	if (divider->flags & CLK_DIVIDER_ONE_BASED)
-		return div_mask(divider);
+		return GENMASK(divider->width - 1, 0);
 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
-		return 1 << div_mask(divider);
+		return 1 << GENMASK(divider->width - 1, 0);
 	if (divider->table)
 		return _get_table_maxdiv(divider->table);
-	return div_mask(divider) + 1;
+	return BIT(divider->width);
 }
 
 static unsigned int _get_table_div(const struct clk_div_table *table,
@@ -103,7 +101,7 @@ static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
 	unsigned int div, val;
 
 	val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
-	val &= div_mask(divider);
+	val &= GENMASK(divider->width - 1, 0);
 
 	div = _get_div(divider, val);
 	if (!div) {
@@ -225,17 +223,17 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 	div = DIV_ROUND_UP(parent_rate, rate);
 	value = _get_val(divider, div);
 
-	if (value > div_mask(divider))
-		value = div_mask(divider);
+	if (value > GENMASK(divider->width - 1, 0))
+		value = GENMASK(divider->width - 1, 0);
 
 	if (divider->lock)
 		spin_lock_irqsave(divider->lock, flags);
 
 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
-		val = div_mask(divider) << (divider->shift + 16);
+		val = GENMASK(divider->width - 1, 0) << (divider->shift + 16);
 	} else {
 		val = ti_clk_ll_ops->clk_readl(divider->reg);
-		val &= ~(div_mask(divider) << divider->shift);
+		val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);
 	}
 	val |= value << divider->shift;
 	ti_clk_ll_ops->clk_writel(val, divider->reg);
-- 
2.1.4

[PATCH v4 5/6] clk: tegra: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/tegra/clk-divider.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 59a5714..bf7f667 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -24,9 +24,8 @@
 #include "clk.h"
 
 #define pll_out_override(p) (BIT((p->shift - 6)))
-#define div_mask(d) ((1 << (d->width)) - 1)
 #define get_mul(d) (1 << d->frac_width)
-#define get_max_div(d) div_mask(d)
+#define get_max_div(d) GENMASK(d->width - 1, 0)
 
 #define PERIPH_CLK_UART_DIV_ENB BIT(24)
 
@@ -73,7 +72,7 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
 	u64 rate = parent_rate;
 
 	reg = readl_relaxed(divider->reg) >> divider->shift;
-	div = reg & div_mask(divider);
+	div = reg & GENMASK(divider->width - 1, 0);
 
 	mul = get_mul(divider);
 	div += mul;
@@ -120,7 +119,7 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
 		spin_lock_irqsave(divider->lock, flags);
 
 	val = readl_relaxed(divider->reg);
-	val &= ~(div_mask(divider) << divider->shift);
+	val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);
 	val |= div << divider->shift;
 
 	if (divider->flags & TEGRA_DIVIDER_UART) {
-- 
2.1.4

[PATCH v4 6/6] ARM: imx: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/arm/mach-imx/clk-fixup-div.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c
index 21db020..cd9a843 100644
--- a/arch/arm/mach-imx/clk-fixup-div.c
+++ b/arch/arm/mach-imx/clk-fixup-div.c
@@ -16,7 +16,6 @@
 #include "clk.h"
 
 #define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
-#define div_mask(d)	((1 << (d->width)) - 1)
 
 /**
  * struct clk_fixup_div - imx integer fixup divider clock
@@ -70,13 +69,13 @@ static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
 	/* Zero based divider */
 	value = divider - 1;
 
-	if (value > div_mask(div))
-		value = div_mask(div);
+	if (value > GENMASK(div->width - 1, 0))
+		value = GENMASK(div->width - 1, 0);
 
 	spin_lock_irqsave(div->lock, flags);
 
 	val = readl(div->reg);
-	val &= ~(div_mask(div) << div->shift);
+	val &= ~(GENMASK(div->width - 1, 0) << div->shift);
 	val |= value << div->shift;
 	fixup_div->fixup(&val);
 	writel(val, div->reg);
-- 
2.1.4

Re: [PATCH v4 3/6] clk: socfpga: switch to GENMASK()

[Dinh Nguyen]

Hi Andy,

On 07/09/2015 11:43 AM, Andy Shevchenko wrote:
> Convert the code to use GENMASK() helper instead of div_mask() macro.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/clk/socfpga/clk-gate.c   | 2 +-
>  drivers/clk/socfpga/clk-periph.c | 2 +-
>  drivers/clk/socfpga/clk.h        | 1 -
>  3 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> index dd3a78c..d61052e 100644
> --- a/drivers/clk/socfpga/clk-gate.c
> +++ b/drivers/clk/socfpga/clk-gate.c
> @@ -110,7 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>  		div = socfpgaclk->fixed_div;
>  	else if (socfpgaclk->div_reg) {
>  		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
> -		val &= div_mask(socfpgaclk->width);
> +		val &= GENMASK(socfpgaclk->width - 1, 0);
>  		/* Check for GPIO_DB_CLK by its offset */
>  		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
>  			div = val + 1;
> diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
> index 46531c3..fc410a4 100644
> --- a/drivers/clk/socfpga/clk-periph.c
> +++ b/drivers/clk/socfpga/clk-periph.c
> @@ -36,7 +36,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
>  	} else {
>  		if (socfpgaclk->div_reg) {
>  			val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
> -			val &= div_mask(socfpgaclk->width);
> +			val &= GENMASK(socfpgaclk->width - 1, 0);
>  			parent_rate /= (val + 1);
>  		}
>  		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
> diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
> index d291f60..5278156 100644
> --- a/drivers/clk/socfpga/clk.h
> +++ b/drivers/clk/socfpga/clk.h
> @@ -27,7 +27,6 @@
>  #define CLKMGR_PERPLL_SRC	0xAC
>  
>  #define SOCFPGA_MAX_PARENTS		3
> -#define div_mask(width) ((1 << (width)) - 1)
>  
>  extern void __iomem *clk_mgr_base_addr;
>  
> 

Thanks for doing this, but this patch did not apply for me on v4.2-rc1.
Also, there are now socfpga/clk-gate-a10.c and socfpga/clk-periph-a10.c
that would also need to use GENMASK. Can you please rebase and resend?

Thanks,
Dinh

Re: [PATCH v4 3/6] clk: socfpga: switch to GENMASK()

[Andy Shevchenko]

On Thu, Jul 9, 2015 at 10:50 PM, Dinh Nguyen
<dinguyen@opensource.altera.com> wrote:
> Hi Andy,
>
> On 07/09/2015 11:43 AM, Andy Shevchenko wrote:
>> Convert the code to use GENMASK() helper instead of div_mask() macro.
>>
>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> ---
>>  drivers/clk/socfpga/clk-gate.c   | 2 +-
>>  drivers/clk/socfpga/clk-periph.c | 2 +-
>>  drivers/clk/socfpga/clk.h        | 1 -
>>  3 files changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
>> index dd3a78c..d61052e 100644
>> --- a/drivers/clk/socfpga/clk-gate.c
>> +++ b/drivers/clk/socfpga/clk-gate.c
>> @@ -110,7 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>>               div = socfpgaclk->fixed_div;
>>       else if (socfpgaclk->div_reg) {
>>               val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
>> -             val &= div_mask(socfpgaclk->width);
>> +             val &= GENMASK(socfpgaclk->width - 1, 0);
>>               /* Check for GPIO_DB_CLK by its offset */
>>               if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
>>                       div = val + 1;
>> diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
>> index 46531c3..fc410a4 100644
>> --- a/drivers/clk/socfpga/clk-periph.c
>> +++ b/drivers/clk/socfpga/clk-periph.c
>> @@ -36,7 +36,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
>>       } else {
>>               if (socfpgaclk->div_reg) {
>>                       val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
>> -                     val &= div_mask(socfpgaclk->width);
>> +                     val &= GENMASK(socfpgaclk->width - 1, 0);
>>                       parent_rate /= (val + 1);
>>               }
>>               div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
>> diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
>> index d291f60..5278156 100644
>> --- a/drivers/clk/socfpga/clk.h
>> +++ b/drivers/clk/socfpga/clk.h
>> @@ -27,7 +27,6 @@
>>  #define CLKMGR_PERPLL_SRC    0xAC
>>
>>  #define SOCFPGA_MAX_PARENTS          3
>> -#define div_mask(width) ((1 << (width)) - 1)
>>
>>  extern void __iomem *clk_mgr_base_addr;
>>
>>
>
> Thanks for doing this, but this patch did not apply for me on v4.2-rc1.
> Also, there are now socfpga/clk-gate-a10.c and socfpga/clk-periph-a10.c
> that would also need to use GENMASK. Can you please rebase and resend?

Ah, usually I'm using linux-next, seems I have to rebase on top of clk
tree. I hope changes you mentioned are there.


-- 
With Best Regards,
Andy Shevchenko