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From: David Daney <ddaney@caviumnetworks.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: David Daney <ddaney.cavm@gmail.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Catalin Marinas <Catalin.Marinas@arm.com>,
	Will Deacon <Will.Deacon@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Robert Richter <rrichter@cavium.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	David Daney <david.daney@cavium.com>
Subject: Re: [PATCH 4/5] irqchip: gic-v3: Add gic_get_irq_domain() to get the irqdomain of the GIC.
Date: Thu, 16 Jul 2015 10:14:11 -0700	[thread overview]
Message-ID: <55A7E663.9030000@caviumnetworks.com> (raw)
In-Reply-To: <55A7E52D.9080201@arm.com>

On 07/16/2015 10:09 AM, Marc Zyngier wrote:
> On 16/07/15 17:50, David Daney wrote:
[...]
>>> Patch 5 has established that you're using "virtual wire" SPIs, so we
>>> need to work on exposing that with the normal kernel abstraction, and
>>> not by messing with the internals of the GIC.
>>>
>>
>> Agreed.
>>
>> The MSI system has pci_enable_msix()/pci_disable_msix().
>>
>> I would propose something like:
>>
>> struct gic_spi_entry {
>> 	int spi   /* SPI number */
>> 	int irq;  /* kernel irq number mapped to the spi*/
>> 	u32 msg;  /* message to be written */
>> 	u64 assert_addr;
>> 	u64 deassert_addr;
>> };
>>
>> /* Fill in the SPI processing information */
>> int gic_map_spi(int spi, struct gic_spi_entry *data);
>
> Neither.
>
> The way to do it is to make this a *separate* IRQ domain stacked onto
> the SPI domain. No funky hook on the side. If it doesn't go through the
> normal kernel API, it doesn't reach the GIC.

Yes, the irqdomain does handle mapping SPI -> irq, and the message can 
be derived from the SPI.  However, the irqdomain infrastructure cannot 
supply values for either assert_addr or deassert_addr.

Those are needed in order to use SPI.  How would you suggest that they 
be obtained?


David Daney


>
> 	M.
>


  reply	other threads:[~2015-07-16 17:14 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-15 16:54 [PATCH 0/5] arm64, pci: Add ECAM/PCIe support for Cavium ThunderX David Daney
2015-07-15 16:54 ` [PATCH 1/5] pci: Add is_pcierc element to struct pci_bus David Daney
2015-07-15 16:54 ` [PATCH 2/5] gic-its: Allow pci_requester_id to be overridden David Daney
2015-07-15 17:30   ` Marc Zyngier
2015-08-20 14:11   ` Pavel Fedin
2015-08-20 15:23     ` David Daney
2015-08-25 11:01       ` Pavel Fedin
2015-07-15 16:54 ` [PATCH 3/5] arm64, pci: Allow RC drivers to supply pcibios_add_device() implementation David Daney
2015-07-16  9:04   ` Lorenzo Pieralisi
2015-07-16 17:00     ` David Daney
2015-07-17 11:00       ` Lorenzo Pieralisi
2015-07-17 16:38         ` David Daney
2015-07-17 17:15           ` Mark Rutland
2015-07-15 16:54 ` [PATCH 4/5] irqchip: gic-v3: Add gic_get_irq_domain() to get the irqdomain of the GIC David Daney
2015-07-15 17:12   ` Marc Zyngier
2015-07-15 18:57     ` David Daney
2015-07-16  7:38       ` Marc Zyngier
2015-07-16 16:50         ` David Daney
2015-07-16 17:09           ` Marc Zyngier
2015-07-16 17:14             ` David Daney [this message]
2015-07-16 17:32               ` Marc Zyngier
2015-07-17  6:45                 ` Marc Zyngier
2015-07-15 16:54 ` [PATCH 5/5] PCI: Add host drivers for Cavium ThunderX processors David Daney
2015-07-15 17:44   ` Mark Rutland
2015-07-15 17:48   ` Marc Zyngier
2015-07-16  8:31   ` Paul Bolle
2015-07-16 16:52     ` David Daney
2015-07-16 13:06   ` Lorenzo Pieralisi
2015-07-17 12:12   ` Arnd Bergmann
2015-07-15 17:07 ` [PATCH 0/5] arm64, pci: Add ECAM/PCIe support for Cavium ThunderX Mark Rutland
2015-07-15 17:29   ` Will Deacon
2015-07-16 17:25 ` Thomas Gleixner

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