From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755617AbbGTMIN (ORCPT ); Mon, 20 Jul 2015 08:08:13 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:46059 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753530AbbGTMHt (ORCPT ); Mon, 20 Jul 2015 08:07:49 -0400 Message-ID: <55ACE4B5.7000107@ti.com> Date: Mon, 20 Jul 2015 15:08:21 +0300 From: Tero Kristo User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Roger Quadros , , CC: , , , , , Subject: Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY References: <1437140844-6032-1-git-send-email-rogerq@ti.com> <1437140844-6032-3-git-send-email-rogerq@ti.com> In-Reply-To: <1437140844-6032-3-git-send-email-rogerq@ti.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/17/2015 04:47 PM, Roger Quadros wrote: > This register is required to be passed to the SATA PHY driver > to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). > > Signed-off-by: Roger Quadros > --- > arch/arm/boot/dts/dra7.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi > index 8f1e25b..4a0718c 100644 > --- a/arch/arm/boot/dts/dra7.dtsi > +++ b/arch/arm/boot/dts/dra7.dtsi > @@ -1140,6 +1140,7 @@ > ctrl-module = <&omap_control_sata>; > clocks = <&sys_clkin1>, <&sata_ref_clk>; > clock-names = "sysclk", "refclk"; > + syscon-pllreset = <&scm_conf 0x3fc>; > #phy-cells = <0>; > }; > > Looks fine to me. Make sure you use this register via regmap_update_bits only, seeing there is another potential user for the same register. -Tero