From: Roger Quadros <rogerq@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Tero Kristo <t-kristo@ti.com>, <tony@atomide.com>
Cc: <nm@ti.com>, <nsekhar@ti.com>, <balbi@ti.com>,
<grygorii.strashko@ti.com>, <linux-omap@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes
Date: Mon, 27 Jul 2015 12:40:59 +0300 [thread overview]
Message-ID: <55B5FCAB.6000808@ti.com> (raw)
In-Reply-To: <55ADD474.6080709@ti.com>
On 21/07/15 08:11, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 20 July 2015 05:34 PM, Tero Kristo wrote:
>> On 07/17/2015 04:47 PM, Roger Quadros wrote:
>>> scm_conf1 maps the control register address space after the
>>> padconf till the end.
>>>
>>> Fix the scm_conf and pmx_core resource lengths. We need to add
>>> 4 bytes to include the last 32-bit register space.
>>>
>>> Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
>>> They are not used by anyone and no longer needed as they are
>>> covered by scm_conf and scm_conf1.
>>
>> Looks like you are doing three things in this patch, maybe split it up
>> as such?
>>
>>>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>> ---
>>> arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
>>> 1 file changed, 8 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>> index 4a0718c..d07c34c 100644
>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>> @@ -141,7 +141,7 @@
>>> dra7_pmx_core: pinmux@1400 {
>>> compatible = "ti,dra7-padconf",
>>> "pinctrl-single";
>>> - reg = <0x1400 0x0464>;
>>> + reg = <0x1400 0x0468>;
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> #interrupt-cells = <1>;
>>> @@ -149,6 +149,13 @@
>>> pinctrl-single,register-width = <32>;
>>> pinctrl-single,function-mask = <0x3fffffff>;
>>> };
>>> +
>>> + scm_conf1: scm_conf@1 {
>>
>> Should be ... scm_conf@1868?
>>
>> Are there any users for this area anyway? I don't think we should map
>> this area just for fun of it. Mostly it looks like this contains efuse
>> values for OPPs, which should be mapped from the OPP layer, not as a
>> generic syscon.
>
> The last few registers are used for PCIe PHY and I'll be needing it for the
> next version of my patch series.
OK noted. Will exclude the PCIe registers from this region.
cheers,
-roger
next prev parent reply other threads:[~2015-07-27 9:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-17 13:47 [PATCH v3 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM (core-retention) Roger Quadros
2015-07-17 13:47 ` [PATCH v3 1/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock Roger Quadros
2015-07-17 13:47 ` [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY Roger Quadros
2015-07-20 12:08 ` Tero Kristo
2015-07-27 9:34 ` Roger Quadros
2015-08-04 8:19 ` Roger Quadros
2015-08-04 8:41 ` Tony Lindgren
2015-08-04 15:43 ` Kishon Vijay Abraham I
2015-07-17 13:47 ` [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes Roger Quadros
2015-07-20 12:04 ` Tero Kristo
2015-07-21 5:11 ` Kishon Vijay Abraham I
2015-07-27 9:40 ` Roger Quadros [this message]
2015-07-27 9:40 ` Roger Quadros
2015-07-27 10:21 ` [PATCH v3 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM (core-retention) Roger Quadros
2015-07-27 10:37 ` Roger Quadros
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