From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754733AbbG3IGw (ORCPT ); Thu, 30 Jul 2015 04:06:52 -0400 Received: from mail-wi0-f169.google.com ([209.85.212.169]:36586 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750770AbbG3IGo (ORCPT ); Thu, 30 Jul 2015 04:06:44 -0400 Message-ID: <55B9DB0E.7010303@gmail.com> Date: Thu, 30 Jul 2015 10:06:38 +0200 From: Sebastian Hesselbarth User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 To: Jisheng Zhang , catalin.marinas@arm.com, will.deacon@arm.com, khilman@linaro.org, arnd@arndb.de, olof@lixom.net, mark.rutland@arm.com, sudeep.holla@arm.com, robh+dt@kernel.org, galak@codeaurora.org, pawel.moll@arm.com CC: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC References: <1437557992-7111-1-git-send-email-jszhang@marvell.com> <1437557992-7111-2-git-send-email-jszhang@marvell.com> In-Reply-To: <1437557992-7111-2-git-send-email-jszhang@marvell.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/22/2015 11:39 AM, Jisheng Zhang wrote: > Add initial dtsi file to support Marvell Berlin4CT SoC with > quad Cortex-A53 CPUs. > > It also adds dts file for Marvell Berlin4CT DMP board which is > based on Berlin4CT SoC. > > Signed-off-by: Jisheng Zhang > --- [...] > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts > new file mode 100644 > index 0000000..d1152c0 > --- /dev/null > +++ b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts > @@ -0,0 +1,66 @@ > +/* > + * Copyright (C) 2015 Marvell Technology Group Ltd. > + * > + * Author: Jisheng Zhang [...] > +/ { Jisheng, before I take this series, some nitpicking. > + model = "MARVELL BG4CT DMP BOARD"; Are you fine with fixing the broken CAPSLOCK key, i.e. make above "Marvell BG4CT DMP board" ? > + compatible = "marvell,berlin4ct-dmp", "marvell,berlin4ct", "marvell,berlin"; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory { > + device_type = "memory"; > + /* the first 16MB is for firmwares's usage */ > + reg = <0 0x01000000 0 0x80000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > new file mode 100644 > index 0000000..becaedc > --- /dev/null > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi > @@ -0,0 +1,164 @@ > +/* > + * Copyright (C) 2015 Marvell Technology Group Ltd. > + * > + * Author: Jisheng Zhang [...] > + > +/ { > + compatible = "marvell,berlin"; compatible = "marvell,berlin4ct", "marvell,berlin"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; [...] > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0xf7000000 0x1000000>; > + > + osc: osc { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + }; Is the oscillator above really part of the SoC bus fabric? If 25MHz is the only option for an external OSC, I suggest to move it at least out of the soc {} node. Sebastian > + gic: interrupt-controller@901000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x901000 0x1000>, > + <0x902000 0x2000>, > + <0x904000 0x2000>, > + <0x906000 0x2000>; > + interrupts = ; > + }; > + > + apb@fc0000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0xfc0000 0x10000>; > + interrupt-parent = <&sic>; > + > + sic: interrupt-controller@1000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x1000 0x30>; > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + uart0: uart@d000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xd000 0x100>; > + interrupts = <8>; > + clocks = <&osc>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + }; > + }; > +}; >