public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: Takao Indoh <indou.takao@jp.fujitsu.com>
To: <tglx@linutronix.de>
Cc: <mingo@redhat.com>, <hpa@zytor.com>, <a.p.zijlstra@chello.nl>,
	<acme@kernel.org>, <alexander.shishkin@linux.intel.com>,
	<vgoyal@redhat.com>, <linux-kernel@vger.kernel.org>,
	<x86@kernel.org>
Subject: Re: [PATCH RFC 1/3] x86: Add Intel PT common files
Date: Mon, 3 Aug 2015 12:14:06 +0900	[thread overview]
Message-ID: <55BEDC7E.9090808@jp.fujitsu.com> (raw)
In-Reply-To: <alpine.DEB.2.11.1508021157520.3825@nanos>

On 2015/08/02 19:02, Thomas Gleixner wrote:
> On Wed, 29 Jul 2015, Takao Indoh wrote:
>> +/*
>> + * Table of Physical Addresses bits
>> + */
>> +enum topa_sz {
>> +	TOPA_4K	= 0,
>> +	TOPA_8K,
>> +	TOPA_16K,
>> +	TOPA_32K,
>> +	TOPA_64K,
>> +	TOPA_128K,
>> +	TOPA_256K,
>> +	TOPA_512K,
>> +	TOPA_1MB,
>> +	TOPA_2MB,
>> +	TOPA_4MB,
>> +	TOPA_8MB,
>> +	TOPA_16MB,
>> +	TOPA_32MB,
>> +	TOPA_64MB,
>> +	TOPA_128MB,
>> +	TOPA_SZ_END,
>> +};
> 
> While moving this around, can we pretty please clean that up? That
> enum just pointless. None of the values is ever used and they hardly
> have any value as they are just computable.

Ok, I'll update my patches based on Alex's comments, but before that
I'll clean up intel_pt.h and perf_event_intel_pt.c.

Thanks,
Takao Indoh

> 
>> +static inline unsigned int sizes(enum topa_sz tsz)
>> +{
>> +	return 1 << (tsz + 12);
> 
> 12?? PAGE_SHIFT perhaps?
> 
>> +#define TOPA_SHIFT 12
> 
> Sigh.
> 
>> diff --git a/arch/x86/kernel/cpu/intel_pt_cap.c b/arch/x86/kernel/cpu/intel_pt_cap.c
>> new file mode 100644
>> index 0000000..a2cfbfc
>> --- /dev/null
>> +++ b/arch/x86/kernel/cpu/intel_pt_cap.c
>> @@ -0,0 +1,69 @@
>> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>> +
>> +#include <linux/mm.h>
>> +#include <asm/intel_pt.h>
>> +
>> +enum cpuid_regs {
>> +	CR_EAX = 0,
>> +	CR_ECX,
>> +	CR_EDX,
>> +	CR_EBX
>> +};
>> +
>> +static u32 cpuid_cache[4 * PT_CPUID_LEAVES];
> 
> 4 ? Magic constant pulled from thin air?
> 
>> +static int pt_cap_initialized;
>> +
>> +#define PT_CAP(_n, _l, _r, _m)						\
>> +	[PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l,	\
>> +			    .reg = _r, .mask = _m }
>> +
>> +static struct pt_cap_desc {
>> +	const char	*name;
>> +	u32		leaf;
>> +	u8		reg;
>> +	u32		mask;
>> +} pt_caps[] = {
>> +	PT_CAP(max_subleaf,		0, CR_EAX, 0xffffffff),
>> +	PT_CAP(cr3_filtering,		0, CR_EBX, BIT(0)),
>> +	PT_CAP(topa_output,		0, CR_ECX, BIT(0)),
>> +	PT_CAP(topa_multiple_entries,	0, CR_ECX, BIT(1)),
>> +	PT_CAP(payloads_lip,		0, CR_ECX, BIT(31)),
>> +};
>> +
>> +u32 pt_cap_get(enum pt_capabilities cap)
>> +{
>> +	struct pt_cap_desc *cd = &pt_caps[cap];
>> +	u32 c = cpuid_cache[cd->leaf * 4 + cd->reg];
> 
> Ditto
> 
>> +	unsigned int shift = __ffs(cd->mask);
>> +
>> +	return (c & cd->mask) >> shift;
>> +}
>> +
>> +const char *pt_cap_name(enum pt_capabilities cap)
>> +{
>> +	return pt_caps[cap].name;
>> +}
>> +
>> +int pt_cap_num(void)
>> +{
>> +	return ARRAY_SIZE(pt_caps);
>> +}
>> +
>> +void __init pt_cap_init(void)
>> +{
>> +	int i;
>> +
>> +	if (pt_cap_initialized)
>> +		return;
>> +
>> +	for (i = 0; i < PT_CPUID_LEAVES; i++) {
>> +		cpuid_count(20, i,
>> +			    &cpuid_cache[CR_EAX + i*4],
> 
> Once more.
> 
> Thanks,
> 
> 	tglx
> 



  reply	other threads:[~2015-08-03  3:14 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-29  4:51 [PATCH RFC 0/3] x86: Intel Processor Trace Logger Takao Indoh
2015-07-29  4:51 ` [PATCH RFC 1/3] x86: Add Intel PT common files Takao Indoh
2015-08-02 10:02   ` Thomas Gleixner
2015-08-03  3:14     ` Takao Indoh [this message]
2015-07-29  4:51 ` [PATCH RFC 2/3] x86: Add Intel PT logger Takao Indoh
2015-07-29  6:08   ` Alexander Shishkin
2015-07-29  8:13     ` Takao Indoh
2015-07-29  9:09       ` Alexander Shishkin
2015-07-30  1:49         ` Takao Indoh
2015-07-30  5:32           ` Alexander Shishkin
2015-08-26  8:10     ` Takao Indoh
2015-07-29  4:51 ` [PATCH RFC 3/3] x86: Stop Intel PT and save its registers when panic occurs Takao Indoh
2015-07-29  5:44 ` [PATCH RFC 0/3] x86: Intel Processor Trace Logger Alexander Shishkin
2015-07-29  5:51   ` Takao Indoh

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=55BEDC7E.9090808@jp.fujitsu.com \
    --to=indou.takao@jp.fujitsu.com \
    --cc=a.p.zijlstra@chello.nl \
    --cc=acme@kernel.org \
    --cc=alexander.shishkin@linux.intel.com \
    --cc=hpa@zytor.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=tglx@linutronix.de \
    --cc=vgoyal@redhat.com \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox