From: Andrew Haley <aph@redhat.com>
To: "Suzuki K. Poulose" <Suzuki.Poulose@arm.com>,
Catalin Marinas <Catalin.Marinas@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Mark Rutland <Mark.Rutland@arm.com>,
Will Deacon <Will.Deacon@arm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"edward.nevill@linaro.org" <edward.nevill@linaro.org>
Subject: Re: [RFC PATCH 01/10] arm64: feature registers: Documentation
Date: Tue, 11 Aug 2015 09:58:00 +0100 [thread overview]
Message-ID: <55C9B918.90807@redhat.com> (raw)
In-Reply-To: <55C9B51D.1060601@arm.com>
On 11/08/15 09:41, Suzuki K. Poulose wrote:
> The REVIDR has to be used in conjunction with the MIDR to make real sense.
Sure, of course.
> We cannot guarantee that the REVIDR that we read (would) belong to the CPU
> where MIDR would have been read (unless the process is pinned) and hence the
> user may not be able to make any use of the information.
Well, yes, nothing is perfect. The situation we're in now, for example,
is that if we see Cortex A57 we have to assume Cortex A53 and include
workarounds. People might mix and match processors. So it goes.
> Steve has a patch [1]
> to expose the MIDR,REVIDR info via sysfs.
>
> [1] https://lkml.org/lkml/2015/7/24/420
OK. As long as I can get at it I'm happy.
Andrew.
next prev parent reply other threads:[~2015-08-11 8:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-24 9:43 [RFC PATCH 00/10] arm64: Expose CPU feature registers Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 01/10] arm64: feature registers: Documentation Suzuki K. Poulose
2015-08-10 16:06 ` Catalin Marinas
2015-08-10 17:36 ` Suzuki K. Poulose
2015-08-10 17:48 ` Ard Biesheuvel
2015-08-11 14:23 ` Catalin Marinas
2015-08-11 15:37 ` Suzuki K. Poulose
2015-09-10 15:55 ` Dave Martin
2015-08-10 18:19 ` Andrew Haley
2015-08-11 8:41 ` Suzuki K. Poulose
2015-08-11 8:58 ` Andrew Haley [this message]
2015-08-11 14:46 ` Catalin Marinas
2015-08-11 15:18 ` Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 02/10] arm64: Make the CPU information more clear Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 03/10] arm64: Delay ELF HWCAP initialisation until all CPUs are up Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 04/10] arm64: Consolidate cpuinfo handling Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 05/10] arm64: Keep track of CPU feature registers Suzuki K. Poulose
2015-08-05 14:58 ` Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 06/10] arm64: Add helper to decode register from instruction Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 07/10] arm64: Expose feature registers by emulating MRS Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 08/10] arm64: Emulate ID registers Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 09/10] arm64: Read system wide CPUID value Suzuki K. Poulose
2015-07-24 9:43 ` [RFC PATCH 10/10] arm64: Use system-wide safe value of CPU feature register Suzuki K. Poulose
2015-07-24 9:43 ` sample: arm64 cpu feature: Test program Suzuki K. Poulose
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