From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752135AbbHMHO3 (ORCPT ); Thu, 13 Aug 2015 03:14:29 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:38154 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750908AbbHMHO1 (ORCPT ); Thu, 13 Aug 2015 03:14:27 -0400 Message-ID: <55CC43B1.4020409@ti.com> Date: Thu, 13 Aug 2015 10:13:53 +0300 From: Roger Quadros User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Tony Lindgren CC: , , , , , , , , , Subject: Re: [PATCH v2 00/22] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms References: <1438938752-31010-1-git-send-email-rogerq@ti.com> <20150811124829.GM4215@atomide.com> In-Reply-To: <20150811124829.GM4215@atomide.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/08/15 15:48, Tony Lindgren wrote: > * Roger Quadros [150807 02:15]: >> Hi, >> >> We do a couple of things in this series which result in >> cleaner device tree implementation, faster perfomance and >> multi-platform support. As an added bonus we get new GPI/Interrupt pins >> for use in the system. >> >> - Establish a custom interface between NAND and GPMC driver. This is >> needed because all of the NAND registers sit in the GPMC register space. >> Some bits like NAND IRQ are even shared with GPMC. >> >> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ >> with the omap2-nand driver and handle NAND IRQ events in the NAND driver. >> This causes performance increase when using prefetch-irq mode. >> 30% increase in read, 17% increase in write in prefetch-irq mode. >> >> - Clean up device tree support so that omap-gpmc IP and the omap2 NAND >> driver can be used on non-OMAP platforms. e.g. Keystone. >> >> - Implement GPIOCHIP + IRQCHIP for the GPMC WAITPINS. SoCs can contain >> 2 to 4 of these and most of them would be unused otherwise. It also >> allows a cleaner implementation of NAND Ready pin status for the NAND driver. >> >> - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver. > > Nice job :) Using GPIOCHIP + IRQCHIP allows us to make the GPMC > using drivers pretty much generic eventually. Thanks :) > >> NOTE: I've only adapted dra7.dtsi and dra7x-evms for this series. >> I will adapt all other boards when the series is in a shape to be accepted. > > OK. Yeah let's make sure no regressions are caused by this.. We also > still have the omap3 legacy booting around, have you checked that it > keeps on working? I don't have any omap3 board with legacy support with me. I have omap3-beagle but looks like legacy boot is dropped for it already. I'll try to revert the patch that drops beagle support and test it on that one. cheers, -roger