From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752006AbbIBNZx (ORCPT ); Wed, 2 Sep 2015 09:25:53 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:5020 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750743AbbIBNZw (ORCPT ); Wed, 2 Sep 2015 09:25:52 -0400 Subject: Re: [PATCH 01/10] irqchip: irq-mips-gic: export gic_send_ipi To: Marc Zyngier , Mark Rutland References: <1440419959-14315-1-git-send-email-qais.yousef@imgtec.com> <1440419959-14315-2-git-send-email-qais.yousef@imgtec.com> <55DB15EB.3090109@imgtec.com> <55DB1CD2.5030300@arm.com> <55DB29B5.3010202@imgtec.com> <55DB48C9.7010508@imgtec.com> <55DB519D.2090203@arm.com> <55DDA1C4.4070301@imgtec.com> <55DDD3E3.7070009@imgtec.com> <55DDDE3C.8030609@imgtec.com> <55E03A2B.3070805@imgtec.com> <55E6C250.50100@imgtec.com> <55E6C788.2000405@arm.com> <55E6D40C.5060708@imgtec.com> <55E6E349.3020907@arm.com> CC: Thomas Gleixner , "alsa-devel@alsa-project.org" , Jason Cooper , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Jiang Liu , Mark Brown , Lisa Parratt From: Qais Yousef Message-ID: <55E6F8DE.7040308@imgtec.com> Date: Wed, 2 Sep 2015 14:25:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <55E6E349.3020907@arm.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.154.94] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/02/2015 12:53 PM, Marc Zyngier wrote: > On 02/09/15 11:48, Qais Yousef wrote: >> It's worth noting in the light of this that INT_SPEC should be optional >> since for hardware similar to mine there's not much to tell the >> controller if it's all dynamic except where we want the IPI to be routed >> to - the INT_SPEC is implicitly defined by the notion it's an IPI. > Well, I'd think that the INT_SPEC should say that it is an IPI, and I > don't believe we should omit it. On the ARM GIC side, our interrupts are > typed (type 0 is a normal wired interrupt, type 1 a per-cpu interrupt, > and we could allocate type 2 to identify an IPI). I didn't mean to omit it completely, but just being optional so it's specified if the intc needs this info only. I'm assuming that INT_SPEC is interrupt controller specific. If not, then ignore me :-) > > But we do need to identify it properly, as we should be able to cover > both IPIs and normal wired interrupts. I'm a bit confused here. What do you mean by normal wired interrupts? I thought this DT binding is only to describe IPIs that needs reserving and routing. What am I missing? Thanks, Qais