* [PATCH 01/21] ARM: common: edma: Fix channel parameter for irq callbacks
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 02/21] ARM: common: edma: Remove unused functions Peter Ujfalusi
` (20 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
In case when the interrupt happened for the second eDMA the channel
number was incorrectly passed to the client driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
CC: <stable@vger.kernel.org>
---
arch/arm/common/edma.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 873dbfcc7dc9..56fc339571f9 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -406,7 +406,8 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
BIT(slot));
if (edma_cc[ctlr]->intr_data[channel].callback)
edma_cc[ctlr]->intr_data[channel].callback(
- channel, EDMA_DMA_COMPLETE,
+ EDMA_CTLR_CHAN(ctlr, channel),
+ EDMA_DMA_COMPLETE,
edma_cc[ctlr]->intr_data[channel].data);
}
} while (sh_ipr);
@@ -460,7 +461,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
if (edma_cc[ctlr]->intr_data[k].
callback) {
edma_cc[ctlr]->intr_data[k].
- callback(k,
+ callback(
+ EDMA_CTLR_CHAN(ctlr, k),
EDMA_DMA_CC_ERROR,
edma_cc[ctlr]->intr_data
[k].data);
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 02/21] ARM: common: edma: Remove unused functions
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 01/21] ARM: common: edma: Fix channel parameter for irq callbacks Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 03/21] dmaengine: edma: Simplify and optimize the edma_execute path Peter Ujfalusi
` (19 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
We no longer have users for these functions so they can be removed.
Remove also unused enums from the header file.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 376 -------------------------------------
include/linux/platform_data/edma.h | 33 ----
2 files changed, 409 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 56fc339571f9..e9c4cb16a47e 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -510,62 +510,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
return IRQ_HANDLED;
}
-static int reserve_contiguous_slots(int ctlr, unsigned int id,
- unsigned int num_slots,
- unsigned int start_slot)
-{
- int i, j;
- unsigned int count = num_slots;
- int stop_slot = start_slot;
- DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
-
- for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
- j = EDMA_CHAN_SLOT(i);
- if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
- /* Record our current beginning slot */
- if (count == num_slots)
- stop_slot = i;
-
- count--;
- set_bit(j, tmp_inuse);
-
- if (count == 0)
- break;
- } else {
- clear_bit(j, tmp_inuse);
-
- if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
- stop_slot = i;
- break;
- } else {
- count = num_slots;
- }
- }
- }
-
- /*
- * We have to clear any bits that we set
- * if we run out parameter RAM slots, i.e we do find a set
- * of contiguous parameter RAM slots but do not find the exact number
- * requested as we may reach the total number of parameter RAM slots
- */
- if (i == edma_cc[ctlr]->num_slots)
- stop_slot = i;
-
- j = start_slot;
- for_each_set_bit_from(j, tmp_inuse, stop_slot)
- clear_bit(j, edma_cc[ctlr]->edma_inuse);
-
- if (count)
- return -EBUSY;
-
- for (j = i - num_slots + 1; j <= i; ++j)
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
- &dummy_paramset, PARM_SIZE);
-
- return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
-}
-
static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -818,186 +762,11 @@ void edma_free_slot(unsigned slot)
}
EXPORT_SYMBOL(edma_free_slot);
-
-/**
- * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
- * The API will return the starting point of a set of
- * contiguous parameter RAM slots that have been requested
- *
- * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
- * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- * @count: number of contiguous Paramter RAM slots
- * @slot - the start value of Parameter RAM slot that should be passed if id
- * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- *
- * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
- * contiguous Parameter RAM slots from parameter RAM 64 in the case of
- * DaVinci SOCs and 32 in the case of DA8xx SOCs.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
- * set of contiguous parameter RAM slots from the "slot" that is passed as an
- * argument to the API.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
- * starts looking for a set of contiguous parameter RAMs from the "slot"
- * that is passed as an argument to the API. On failure the API will try to
- * find a set of contiguous Parameter RAM slots from the remaining Parameter
- * RAM slots
- */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
-{
- /*
- * The start slot requested should be greater than
- * the number of channels and lesser than the total number
- * of slots
- */
- if ((id != EDMA_CONT_PARAMS_ANY) &&
- (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots))
- return -EINVAL;
-
- /*
- * The number of parameter RAM slots requested cannot be less than 1
- * and cannot be more than the number of slots minus the number of
- * channels
- */
- if (count < 1 || count >
- (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
- return -EINVAL;
-
- switch (id) {
- case EDMA_CONT_PARAMS_ANY:
- return reserve_contiguous_slots(ctlr, id, count,
- edma_cc[ctlr]->num_channels);
- case EDMA_CONT_PARAMS_FIXED_EXACT:
- case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
- return reserve_contiguous_slots(ctlr, id, count, slot);
- default:
- return -EINVAL;
- }
-
-}
-EXPORT_SYMBOL(edma_alloc_cont_slots);
-
-/**
- * edma_free_cont_slots - deallocate DMA parameter RAM slots
- * @slot: first parameter RAM of a set of parameter RAM slots to be freed
- * @count: the number of contiguous parameter RAM slots to be freed
- *
- * This deallocates the parameter RAM slots allocated by
- * edma_alloc_cont_slots.
- * Callers/applications need to keep track of sets of contiguous
- * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
- * API.
- * Callers are responsible for ensuring the slots are inactive, and will
- * not be activated.
- */
-int edma_free_cont_slots(unsigned slot, int count)
-{
- unsigned ctlr, slot_to_free;
- int i;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots ||
- count < 1)
- return -EINVAL;
-
- for (i = slot; i < slot + count; ++i) {
- ctlr = EDMA_CTLR(i);
- slot_to_free = EDMA_CHAN_SLOT(i);
-
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
- &dummy_paramset, PARM_SIZE);
- clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
- }
-
- return 0;
-}
-EXPORT_SYMBOL(edma_free_cont_slots);
-
/*-----------------------------------------------------------------------*/
/* Parameter RAM operations (i) -- read/write partial slots */
/**
- * edma_set_src - set initial DMA source address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @src_port: physical address of source (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the source address is modified during the DMA transfer
- * according to edma_set_src_index().
- */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set SAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
- } else {
- /* clear SAM */
- i &= ~SAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
-
- /* set the source port address
- in source register of param structure */
- edma_parm_write(ctlr, PARM_SRC, slot, src_port);
- }
-}
-EXPORT_SYMBOL(edma_set_src);
-
-/**
- * edma_set_dest - set initial DMA destination address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @dest_port: physical address of destination (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the destination address is modified during the DMA transfer
- * according to edma_set_dest_index().
- */
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set DAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
- } else {
- /* clear DAM */
- i &= ~DAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
- /* set the destination port address
- in dest register of param structure */
- edma_parm_write(ctlr, PARM_DST, slot, dest_port);
- }
-}
-EXPORT_SYMBOL(edma_set_dest);
-
-/**
* edma_get_position - returns the current transfer point
* @slot: parameter RAM slot being examined
* @dst: true selects the dest position, false the source
@@ -1017,110 +786,6 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
}
/**
- * edma_set_src_index - configure DMA source address indexing
- * @slot: parameter RAM slot being configured
- * @src_bidx: byte offset between source arrays in a frame
- * @src_cidx: byte offset between source frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0xffff0000, src_bidx);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0xffff0000, src_cidx);
- }
-}
-EXPORT_SYMBOL(edma_set_src_index);
-
-/**
- * edma_set_dest_index - configure DMA destination address indexing
- * @slot: parameter RAM slot being configured
- * @dest_bidx: byte offset between destination arrays in a frame
- * @dest_cidx: byte offset between destination frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0x0000ffff, dest_bidx << 16);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0x0000ffff, dest_cidx << 16);
- }
-}
-EXPORT_SYMBOL(edma_set_dest_index);
-
-/**
- * edma_set_transfer_params - configure DMA transfer parameters
- * @slot: parameter RAM slot being configured
- * @acnt: how many bytes per array (at least one)
- * @bcnt: how many arrays per frame (at least one)
- * @ccnt: how many frames per block (at least one)
- * @bcnt_rld: used only for A-Synchronized transfers; this specifies
- * the value to reload into bcnt when it decrements to zero
- * @sync_mode: ASYNC or ABSYNC
- *
- * See the EDMA3 documentation to understand how to configure and link
- * transfers using the fields in PaRAM slots. If you are not doing it
- * all at once with edma_write_slot(), you will use this routine
- * plus two calls each for source and destination, setting the initial
- * address and saying how to index that address.
- *
- * An example of an A-Synchronized transfer is a serial link using a
- * single word shift register. In that case, @acnt would be equal to
- * that word size; the serial controller issues a DMA synchronization
- * event to transfer each word, and memory access by the DMA transfer
- * controller will be word-at-a-time.
- *
- * An example of an AB-Synchronized transfer is a device using a FIFO.
- * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
- * The controller with the FIFO issues DMA synchronization events when
- * the FIFO threshold is reached, and the DMA transfer controller will
- * transfer one frame to (or from) the FIFO. It will probably use
- * efficient burst modes to access memory.
- */
-void edma_set_transfer_params(unsigned slot,
- u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
- 0x0000ffff, bcnt_rld << 16);
- if (sync_mode == ASYNC)
- edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
- else
- edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
- /* Set the acount, bcount, ccount registers */
- edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
- edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
- }
-}
-EXPORT_SYMBOL(edma_set_transfer_params);
-
-/**
* edma_link - link one parameter RAM slot to another
* @from: parameter RAM slot originating the link
* @to: parameter RAM slot which is the link target
@@ -1145,26 +810,6 @@ void edma_link(unsigned from, unsigned to)
}
EXPORT_SYMBOL(edma_link);
-/**
- * edma_unlink - cut link from one parameter RAM slot
- * @from: parameter RAM slot originating the link
- *
- * The originating slot should not be part of any active DMA transfer.
- * Its link is set to 0xffff.
- */
-void edma_unlink(unsigned from)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(from);
- from = EDMA_CHAN_SLOT(from);
-
- if (from >= edma_cc[ctlr]->num_slots)
- return;
- edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
-}
-EXPORT_SYMBOL(edma_unlink);
-
/*-----------------------------------------------------------------------*/
/* Parameter RAM operations (ii) -- read/write whole parameter sets */
@@ -1402,27 +1047,6 @@ void edma_clean_channel(unsigned channel)
EXPORT_SYMBOL(edma_clean_channel);
/*
- * edma_clear_event - clear an outstanding event on the DMA channel
- * Arguments:
- * channel - channel number
- */
-void edma_clear_event(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel >= edma_cc[ctlr]->num_channels)
- return;
- if (channel < 32)
- edma_write(ctlr, EDMA_ECR, BIT(channel));
- else
- edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
-}
-EXPORT_SYMBOL(edma_clear_event);
-
-/*
* edma_assign_channel_eventq - move given channel to desired eventq
* Arguments:
* channel - channel number
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index bdb2710e2aab..c1862423b356 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -72,20 +72,6 @@ struct edmacc_param {
#define EDMA_DMA_TC1_ERROR 3
#define EDMA_DMA_TC2_ERROR 4
-enum address_mode {
- INCR = 0,
- FIFO = 1
-};
-
-enum fifo_width {
- W8BIT = 0,
- W16BIT = 1,
- W32BIT = 2,
- W64BIT = 3,
- W128BIT = 4,
- W256BIT = 5
-};
-
enum dma_event_q {
EVENTQ_0 = 0,
EVENTQ_1 = 1,
@@ -94,11 +80,6 @@ enum dma_event_q {
EVENTQ_DEFAULT = -1
};
-enum sync_dimension {
- ASYNC = 0,
- ABSYNC = 1
-};
-
#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
#define EDMA_CTLR(i) ((i) >> 16)
#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
@@ -121,22 +102,9 @@ void edma_free_channel(unsigned channel);
int edma_alloc_slot(unsigned ctlr, int slot);
void edma_free_slot(unsigned slot);
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width);
dma_addr_t edma_get_position(unsigned slot, bool dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode);
void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
/* calls that operate on an entire parameter RAM slot */
void edma_write_slot(unsigned slot, const struct edmacc_param *params);
@@ -146,7 +114,6 @@ void edma_read_slot(unsigned slot, struct edmacc_param *params);
int edma_start(unsigned channel);
void edma_stop(unsigned channel);
void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
void edma_pause(unsigned channel);
void edma_resume(unsigned channel);
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 03/21] dmaengine: edma: Simplify and optimize the edma_execute path
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 01/21] ARM: common: edma: Fix channel parameter for irq callbacks Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 02/21] ARM: common: edma: Remove unused functions Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 04/21] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver Peter Ujfalusi
` (18 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
The code path in edma_execute() and edma_callback() can be simplified
and make it more optimal.
There is not need to call in to edma_execute() when the transfer
has been finished for example.
Also the handling of missed/first or next batch of paRAMs can
be done in a more optimal way.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 76 +++++++++++++++++++++---------------------------------
1 file changed, 29 insertions(+), 47 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 3e5d4f193005..19fa49d6f555 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -154,15 +154,11 @@ static void edma_execute(struct edma_chan *echan)
struct device *dev = echan->vchan.chan.device->dev;
int i, j, left, nslots;
- /* If either we processed all psets or we're still not started */
- if (!echan->edesc ||
- echan->edesc->pset_nr == echan->edesc->processed) {
- /* Get next vdesc */
+ if (!echan->edesc) {
+ /* Setup is needed for the first transfer */
vdesc = vchan_next_desc(&echan->vchan);
- if (!vdesc) {
- echan->edesc = NULL;
+ if (!vdesc)
return;
- }
list_del(&vdesc->node);
echan->edesc = to_edma_desc(&vdesc->tx);
}
@@ -220,28 +216,26 @@ static void edma_execute(struct edma_chan *echan)
echan->ecc->dummy_slot);
}
- if (edesc->processed <= MAX_NR_SG) {
- dev_dbg(dev, "first transfer starting on channel %d\n",
- echan->ch_num);
- edma_start(echan->ch_num);
- } else {
- dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
- echan->ch_num, edesc->processed);
- edma_resume(echan->ch_num);
- }
-
- /*
- * This happens due to setup times between intermediate transfers
- * in long SG lists which have to be broken up into transfers of
- * MAX_NR_SG
- */
if (echan->missed) {
+ /*
+ * This happens due to setup times between intermediate
+ * transfers in long SG lists which have to be broken up into
+ * transfers of MAX_NR_SG
+ */
dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
edma_clean_channel(echan->ch_num);
edma_stop(echan->ch_num);
edma_start(echan->ch_num);
edma_trigger_channel(echan->ch_num);
echan->missed = 0;
+ } else if (edesc->processed <= MAX_NR_SG) {
+ dev_dbg(dev, "first transfer starting on channel %d\n",
+ echan->ch_num);
+ edma_start(echan->ch_num);
+ } else {
+ dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
+ echan->ch_num, edesc->processed);
+ edma_resume(echan->ch_num);
}
}
@@ -259,20 +253,17 @@ static int edma_terminate_all(struct dma_chan *chan)
* echan->edesc is NULL and exit.)
*/
if (echan->edesc) {
- int cyclic = echan->edesc->cyclic;
-
+ edma_stop(echan->ch_num);
+ /* Move the cyclic channel back to default queue */
+ if (echan->edesc->cyclic)
+ edma_assign_channel_eventq(echan->ch_num,
+ EVENTQ_DEFAULT);
/*
* free the running request descriptor
* since it is not in any of the vdesc lists
*/
edma_desc_free(&echan->edesc->vdesc);
-
echan->edesc = NULL;
- edma_stop(echan->ch_num);
- /* Move the cyclic channel back to default queue */
- if (cyclic)
- edma_assign_channel_eventq(echan->ch_num,
- EVENTQ_DEFAULT);
}
vchan_get_all_descriptors(&echan->vchan, &head);
@@ -725,41 +716,33 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
edesc = echan->edesc;
- /* Pause the channel for non-cyclic */
- if (!edesc || (edesc && !edesc->cyclic))
- edma_pause(echan->ch_num);
-
+ spin_lock(&echan->vchan.lock);
switch (ch_status) {
case EDMA_DMA_COMPLETE:
- spin_lock(&echan->vchan.lock);
-
if (edesc) {
if (edesc->cyclic) {
vchan_cyclic_callback(&edesc->vdesc);
+ goto out;
} else if (edesc->processed == edesc->pset_nr) {
dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
edesc->residue = 0;
edma_stop(echan->ch_num);
vchan_cookie_complete(&edesc->vdesc);
- edma_execute(echan);
+ echan->edesc = NULL;
} else {
dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
+ edma_pause(echan->ch_num);
+
/* Update statistics for tx_status */
edesc->residue -= edesc->sg_len;
edesc->residue_stat = edesc->residue;
edesc->processed_stat = edesc->processed;
-
- edma_execute(echan);
}
+ edma_execute(echan);
}
-
- spin_unlock(&echan->vchan.lock);
-
break;
case EDMA_DMA_CC_ERROR:
- spin_lock(&echan->vchan.lock);
-
edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
/*
@@ -788,13 +771,12 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
edma_start(echan->ch_num);
edma_trigger_channel(echan->ch_num);
}
-
- spin_unlock(&echan->vchan.lock);
-
break;
default:
break;
}
+out:
+ spin_unlock(&echan->vchan.lock);
}
/* Alloc channel resources */
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 04/21] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (2 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 03/21] dmaengine: edma: Simplify and optimize the edma_execute path Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 05/21] ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver Peter Ujfalusi
` (17 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Currently we have one device created to handle all (maximum 2) eDMAs in the
system.
With this change all eDMA instance will have it's own device/driver.
This change is needed for further cleanups in the eDMA driver stack since
the one device/driver to handle all eDMAs in the system was not flexible
enough and prevents the upcoming work.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 357 +++++++++++++++-------------------
arch/arm/mach-davinci/devices-da8xx.c | 110 ++++-------
arch/arm/mach-davinci/dm355.c | 21 +-
arch/arm/mach-davinci/dm365.c | 25 +--
arch/arm/mach-davinci/dm644x.c | 21 +-
arch/arm/mach-davinci/dm646x.c | 27 ++-
6 files changed, 235 insertions(+), 326 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index e9c4cb16a47e..72fce68a959f 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -235,6 +235,7 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
/* actual number of DMA channels and slots on this silicon */
struct edma {
+ struct device *dev;
/* how many dma resources of each type */
unsigned num_channels;
unsigned num_region;
@@ -246,6 +247,7 @@ struct edma {
const s8 *noevent;
struct edma_soc_info *info;
+ int id;
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
@@ -258,9 +260,6 @@ struct edma {
*/
DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
- unsigned irq_res_start;
- unsigned irq_res_end;
-
struct dma_interrupt_data {
void (*callback)(unsigned channel, unsigned short ch_status,
void *data);
@@ -349,17 +348,6 @@ setup_dma_interrupt(unsigned lch,
}
}
-static int irq2ctlr(int irq)
-{
- if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
- return 0;
- else if (irq >= edma_cc[1]->irq_res_start &&
- irq <= edma_cc[1]->irq_res_end)
- return 1;
-
- return -1;
-}
-
/******************************************************************************
*
* DMA interrupt handler
@@ -367,16 +355,17 @@ static int irq2ctlr(int irq)
*****************************************************************************/
static irqreturn_t dma_irq_handler(int irq, void *data)
{
+ struct edma *cc = data;
int ctlr;
u32 sh_ier;
u32 sh_ipr;
u32 bank;
- ctlr = irq2ctlr(irq);
+ ctlr = cc->id;
if (ctlr < 0)
return IRQ_NONE;
- dev_dbg(data, "dma_irq_handler\n");
+ dev_dbg(cc->dev, "dma_irq_handler\n");
sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
if (!sh_ipr) {
@@ -394,7 +383,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
u32 slot;
u32 channel;
- dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
+ dev_dbg(cc->dev, "IPR%d %08x\n", bank, sh_ipr);
slot = __ffs(sh_ipr);
sh_ipr &= ~(BIT(slot));
@@ -404,11 +393,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, bank,
BIT(slot));
- if (edma_cc[ctlr]->intr_data[channel].callback)
- edma_cc[ctlr]->intr_data[channel].callback(
+ if (cc->intr_data[channel].callback)
+ cc->intr_data[channel].callback(
EDMA_CTLR_CHAN(ctlr, channel),
EDMA_DMA_COMPLETE,
- edma_cc[ctlr]->intr_data[channel].data);
+ cc->intr_data[channel].data);
}
} while (sh_ipr);
@@ -423,15 +412,16 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
*****************************************************************************/
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
+ struct edma *cc = data;
int i;
int ctlr;
unsigned int cnt = 0;
- ctlr = irq2ctlr(irq);
+ ctlr = cc->id;
if (ctlr < 0)
return IRQ_NONE;
- dev_dbg(data, "dma_ccerr_handler\n");
+ dev_dbg(cc->dev, "dma_ccerr_handler\n");
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
@@ -446,8 +436,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
else if (edma_read_array(ctlr, EDMA_EMR, 1))
j = 1;
if (j >= 0) {
- dev_dbg(data, "EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
+ dev_dbg(cc->dev, "EMR%d %08x\n", j,
+ edma_read_array(ctlr, EDMA_EMR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
if (edma_read_array(ctlr, EDMA_EMR, j) &
@@ -458,19 +448,16 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR,
j, BIT(i));
- if (edma_cc[ctlr]->intr_data[k].
- callback) {
- edma_cc[ctlr]->intr_data[k].
- callback(
- EDMA_CTLR_CHAN(ctlr, k),
- EDMA_DMA_CC_ERROR,
- edma_cc[ctlr]->intr_data
- [k].data);
+ if (cc->intr_data[k].callback) {
+ cc->intr_data[k].callback(
+ EDMA_CTLR_CHAN(ctlr, k),
+ EDMA_DMA_CC_ERROR,
+ cc->intr_data[k].data);
}
}
}
} else if (edma_read(ctlr, EDMA_QEMR)) {
- dev_dbg(data, "QEMR %02x\n",
+ dev_dbg(cc->dev, "QEMR %02x\n",
edma_read(ctlr, EDMA_QEMR));
for (i = 0; i < 8; i++) {
if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
@@ -483,7 +470,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
}
}
} else if (edma_read(ctlr, EDMA_CCERR)) {
- dev_dbg(data, "CCERR %08x\n",
+ dev_dbg(cc->dev, "CCERR %08x\n",
edma_read(ctlr, EDMA_CCERR));
/* FIXME: CCERR.BIT(16) ignored! much better
* to just write CCERRCLR with CCERR value...
@@ -1239,21 +1226,19 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
static int edma_probe(struct platform_device *pdev)
{
- struct edma_soc_info **info = pdev->dev.platform_data;
- struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
+ struct edma_soc_info *info = pdev->dev.platform_data;
s8 (*queue_priority_mapping)[2];
- int i, j, off, ln, found = 0;
- int status = -1;
+ int i, off, ln;
const s16 (*rsv_chans)[2];
const s16 (*rsv_slots)[2];
const s16 (*xbar_chans)[2];
- int irq[EDMA_MAX_CC] = {0, 0};
- int err_irq[EDMA_MAX_CC] = {0, 0};
- struct resource *r[EDMA_MAX_CC] = {NULL};
- struct resource res[EDMA_MAX_CC];
- char res_name[10];
+ int irq;
+ char *irq_name;
+ struct resource *mem;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
+ int dev_id = pdev->id;
+ struct edma *cc;
int ret;
struct platform_device_info edma_dev_info = {
.name = "edma-dma-engine",
@@ -1261,6 +1246,17 @@ static int edma_probe(struct platform_device *pdev)
.parent = &pdev->dev,
};
+ /* When booting with DT the pdev->id is -1 */
+ if (dev_id < 0)
+ dev_id = arch_num_cc;
+
+ if (dev_id >= EDMA_MAX_CC) {
+ dev_err(dev,
+ "eDMA3 with device id 0 and 1 is supported (id: %d)\n",
+ dev_id);
+ return -EINVAL;
+ }
+
if (node) {
/* Check if this is a second instance registered */
if (arch_num_cc) {
@@ -1268,13 +1264,11 @@ static int edma_probe(struct platform_device *pdev)
return -ENODEV;
}
- ninfo[0] = edma_setup_info_from_dt(dev, node);
- if (IS_ERR(ninfo[0])) {
+ info = edma_setup_info_from_dt(dev, node);
+ if (IS_ERR(info)) {
dev_err(dev, "failed to get DT data\n");
- return PTR_ERR(ninfo[0]);
+ return PTR_ERR(info);
}
-
- info = ninfo;
}
if (!info)
@@ -1287,154 +1281,133 @@ static int edma_probe(struct platform_device *pdev)
return ret;
}
- for (j = 0; j < EDMA_MAX_CC; j++) {
- if (!info[j]) {
- if (!found)
- return -ENODEV;
- break;
- }
- if (node) {
- ret = of_address_to_resource(node, j, &res[j]);
- if (!ret)
- r[j] = &res[j];
- } else {
- sprintf(res_name, "edma_cc%d", j);
- r[j] = platform_get_resource_byname(pdev,
- IORESOURCE_MEM,
- res_name);
- }
- if (!r[j]) {
- if (found)
- break;
- else
- return -ENODEV;
- } else {
- found = 1;
+ mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
+ if (!mem) {
+ dev_dbg(dev, "mem resource not found, using index 0\n");
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem) {
+ dev_err(dev, "no mem resource?\n");
+ return -ENODEV;
}
+ }
- edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
- if (IS_ERR(edmacc_regs_base[j]))
- return PTR_ERR(edmacc_regs_base[j]);
+ edmacc_regs_base[dev_id] = devm_ioremap_resource(dev, mem);
+ if (IS_ERR(edmacc_regs_base[dev_id]))
+ return PTR_ERR(edmacc_regs_base[dev_id]);
- edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
- GFP_KERNEL);
- if (!edma_cc[j])
- return -ENOMEM;
+ edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
+ if (!edma_cc[dev_id])
+ return -ENOMEM;
- /* Get eDMA3 configuration from IP */
- ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
- if (ret)
- return ret;
+ cc = edma_cc[dev_id];
+ cc->dev = dev;
+ cc->id = dev_id;
+ dev_set_drvdata(dev, cc);
- edma_cc[j]->default_queue = info[j]->default_queue;
+ /* Get eDMA3 configuration from IP */
+ ret = edma_setup_from_hw(dev, info, cc, dev_id);
+ if (ret)
+ return ret;
- dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
- edmacc_regs_base[j]);
+ cc->default_queue = info->default_queue;
- for (i = 0; i < edma_cc[j]->num_slots; i++)
- memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
- &dummy_paramset, PARM_SIZE);
+ dev_dbg(dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[dev_id]);
- /* Mark all channels as unused */
- memset(edma_cc[j]->edma_unused, 0xff,
- sizeof(edma_cc[j]->edma_unused));
+ for (i = 0; i < cc->num_slots; i++)
+ memcpy_toio(edmacc_regs_base[dev_id] + PARM_OFFSET(i),
+ &dummy_paramset, PARM_SIZE);
- if (info[j]->rsv) {
+ /* Mark all channels as unused */
+ memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused));
- /* Clear the reserved channels in unused list */
- rsv_chans = info[j]->rsv->rsv_chans;
- if (rsv_chans) {
- for (i = 0; rsv_chans[i][0] != -1; i++) {
- off = rsv_chans[i][0];
- ln = rsv_chans[i][1];
- clear_bits(off, ln,
- edma_cc[j]->edma_unused);
- }
- }
+ if (info->rsv) {
- /* Set the reserved slots in inuse list */
- rsv_slots = info[j]->rsv->rsv_slots;
- if (rsv_slots) {
- for (i = 0; rsv_slots[i][0] != -1; i++) {
- off = rsv_slots[i][0];
- ln = rsv_slots[i][1];
- set_bits(off, ln,
- edma_cc[j]->edma_inuse);
- }
+ /* Clear the reserved channels in unused list */
+ rsv_chans = info->rsv->rsv_chans;
+ if (rsv_chans) {
+ for (i = 0; rsv_chans[i][0] != -1; i++) {
+ off = rsv_chans[i][0];
+ ln = rsv_chans[i][1];
+ clear_bits(off, ln, cc->edma_unused);
}
}
- /* Clear the xbar mapped channels in unused list */
- xbar_chans = info[j]->xbar_chans;
- if (xbar_chans) {
- for (i = 0; xbar_chans[i][1] != -1; i++) {
- off = xbar_chans[i][1];
- clear_bits(off, 1,
- edma_cc[j]->edma_unused);
+ /* Set the reserved slots in inuse list */
+ rsv_slots = info->rsv->rsv_slots;
+ if (rsv_slots) {
+ for (i = 0; rsv_slots[i][0] != -1; i++) {
+ off = rsv_slots[i][0];
+ ln = rsv_slots[i][1];
+ set_bits(off, ln, cc->edma_inuse);
}
}
+ }
- if (node) {
- irq[j] = irq_of_parse_and_map(node, 0);
- err_irq[j] = irq_of_parse_and_map(node, 2);
- } else {
- char irq_name[10];
-
- sprintf(irq_name, "edma%d", j);
- irq[j] = platform_get_irq_byname(pdev, irq_name);
-
- sprintf(irq_name, "edma%d_err", j);
- err_irq[j] = platform_get_irq_byname(pdev, irq_name);
- }
- edma_cc[j]->irq_res_start = irq[j];
- edma_cc[j]->irq_res_end = err_irq[j];
-
- status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
- "edma", dev);
- if (status < 0) {
- dev_dbg(&pdev->dev,
- "devm_request_irq %d failed --> %d\n",
- irq[j], status);
- return status;
+ /* Clear the xbar mapped channels in unused list */
+ xbar_chans = info->xbar_chans;
+ if (xbar_chans) {
+ for (i = 0; xbar_chans[i][1] != -1; i++) {
+ off = xbar_chans[i][1];
+ clear_bits(off, 1, cc->edma_unused);
}
+ }
- status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
- "edma_error", dev);
- if (status < 0) {
- dev_dbg(&pdev->dev,
- "devm_request_irq %d failed --> %d\n",
- err_irq[j], status);
- return status;
+ irq = platform_get_irq_byname(pdev, "edma3_ccint");
+ if (irq < 0 && node)
+ irq = irq_of_parse_and_map(node, 0);
+
+ if (irq >= 0) {
+ irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint\n",
+ dev_name(dev));
+ ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
+ cc);
+ if (ret) {
+ dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
+ return ret;
}
+ }
- for (i = 0; i < edma_cc[j]->num_channels; i++)
- map_dmach_queue(j, i, info[j]->default_queue);
+ irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
+ if (irq < 0 && node)
+ irq = irq_of_parse_and_map(node, 2);
+
+ if (irq >= 0) {
+ irq_name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s_ccerrint\n",
+ dev_name(dev));
+ ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
+ cc);
+ if (ret) {
+ dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
+ return ret;
+ }
+ }
- queue_priority_mapping = info[j]->queue_priority_mapping;
+ for (i = 0; i < cc->num_channels; i++)
+ map_dmach_queue(dev_id, i, info->default_queue);
- /* Event queue priority mapping */
- for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(j,
- queue_priority_mapping[i][0],
- queue_priority_mapping[i][1]);
+ queue_priority_mapping = info->queue_priority_mapping;
- /* Map the channel to param entry if channel mapping logic
- * exist
- */
- if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(j);
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(dev_id, queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
- for (i = 0; i < edma_cc[j]->num_region; i++) {
- edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
- edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
- edma_write_array(j, EDMA_QRAE, i, 0x0);
- }
- edma_cc[j]->info = info[j];
- arch_num_cc++;
+ /* Map the channel to param entry if channel mapping logic exist */
+ if (edma_read(dev_id, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(dev_id);
- edma_dev_info.id = j;
- platform_device_register_full(&edma_dev_info);
+ for (i = 0; i < cc->num_region; i++) {
+ edma_write_array2(dev_id, EDMA_DRAE, i, 0, 0x0);
+ edma_write_array2(dev_id, EDMA_DRAE, i, 1, 0x0);
+ edma_write_array(dev_id, EDMA_QRAE, i, 0x0);
}
+ cc->info = info;
+ arch_num_cc++;
+
+ edma_dev_info.id = dev_id;
+
+ platform_device_register_full(&edma_dev_info);
return 0;
}
@@ -1442,38 +1415,30 @@ static int edma_probe(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int edma_pm_resume(struct device *dev)
{
- int i, j;
+ struct edma *cc = dev_get_drvdata(dev);
+ int i;
+ s8 (*queue_priority_mapping)[2];
- for (j = 0; j < arch_num_cc; j++) {
- struct edma *cc = edma_cc[j];
+ queue_priority_mapping = cc->info->queue_priority_mapping;
- s8 (*queue_priority_mapping)[2];
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(cc->id, queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
- queue_priority_mapping = cc->info->queue_priority_mapping;
+ /* Map the channel to param entry if channel mapping logic */
+ if (edma_read(cc->id, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(cc->id);
- /* Event queue priority mapping */
- for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(j,
- queue_priority_mapping[i][0],
- queue_priority_mapping[i][1]);
+ for (i = 0; i < cc->num_channels; i++) {
+ if (test_bit(i, cc->edma_inuse)) {
+ /* ensure access through shadow region 0 */
+ edma_or_array2(cc->id, EDMA_DRAE, 0, i >> 5,
+ BIT(i & 0x1f));
- /*
- * Map the channel to param entry if channel mapping logic
- * exist
- */
- if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(j);
-
- for (i = 0; i < cc->num_channels; i++) {
- if (test_bit(i, cc->edma_inuse)) {
- /* ensure access through shadow region 0 */
- edma_or_array2(j, EDMA_DRAE, 0, i >> 5,
- BIT(i & 0x1f));
-
- setup_dma_interrupt(i,
- cc->intr_data[i].callback,
- cc->intr_data[i].data);
- }
+ setup_dma_interrupt(EDMA_CTLR_CHAN(cc->id, i),
+ cc->intr_data[i].callback,
+ cc->intr_data[i].data);
}
}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 29e08aac8294..9ae049ae816a 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -147,150 +147,114 @@ static s8 da850_queue_priority_mapping[][2] = {
{-1, -1}
};
-static struct edma_soc_info da830_edma_cc0_info = {
+static struct edma_soc_info da8xx_edma0_pdata = {
.queue_priority_mapping = da8xx_queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
- &da830_edma_cc0_info,
+static struct edma_soc_info da850_edma1_pdata = {
+ .queue_priority_mapping = da850_queue_priority_mapping,
+ .default_queue = EVENTQ_0,
};
-static struct edma_soc_info da850_edma_cc_info[] = {
+static struct resource da8xx_edma0_resources[] = {
{
- .queue_priority_mapping = da8xx_queue_priority_mapping,
- .default_queue = EVENTQ_1,
- },
- {
- .queue_priority_mapping = da850_queue_priority_mapping,
- .default_queue = EVENTQ_0,
- },
-};
-
-static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
- &da850_edma_cc_info[0],
- &da850_edma_cc_info[1],
-};
-
-static struct resource da830_edma_resources[] = {
- {
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = DA8XX_TPCC_BASE,
.end = DA8XX_TPCC_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = DA8XX_TPTC0_BASE,
.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = DA8XX_TPTC1_BASE,
.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_DA8XX_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_DA8XX_CCERRINT,
.flags = IORESOURCE_IRQ,
},
};
-static struct resource da850_edma_resources[] = {
- {
- .name = "edma_cc0",
- .start = DA8XX_TPCC_BASE,
- .end = DA8XX_TPCC_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma_tc0",
- .start = DA8XX_TPTC0_BASE,
- .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
+static struct resource da850_edma1_resources[] = {
{
- .name = "edma_tc1",
- .start = DA8XX_TPTC1_BASE,
- .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma_cc1",
+ .name = "edma3_cc",
.start = DA850_TPCC1_BASE,
.end = DA850_TPCC1_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc2",
+ .name = "edma3_tc0",
.start = DA850_TPTC2_BASE,
.end = DA850_TPTC2_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
- .start = IRQ_DA8XX_CCINT0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma0_err",
- .start = IRQ_DA8XX_CCERRINT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma1",
+ .name = "edma3_ccint",
.start = IRQ_DA850_CCINT1,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma1_err",
+ .name = "edma3_ccerrint",
.start = IRQ_DA850_CCERRINT1,
.flags = IORESOURCE_IRQ,
},
};
-static struct platform_device da830_edma_device = {
+static struct platform_device da8xx_edma0_device = {
.name = "edma",
- .id = -1,
+ .id = 0,
.dev = {
- .platform_data = da830_edma_info,
+ .platform_data = &da8xx_edma0_pdata,
},
- .num_resources = ARRAY_SIZE(da830_edma_resources),
- .resource = da830_edma_resources,
+ .num_resources = ARRAY_SIZE(da8xx_edma0_resources),
+ .resource = da8xx_edma0_resources,
};
-static struct platform_device da850_edma_device = {
+static struct platform_device da850_edma1_device = {
.name = "edma",
- .id = -1,
+ .id = 1,
.dev = {
- .platform_data = da850_edma_info,
+ .platform_data = &da850_edma1_pdata,
},
- .num_resources = ARRAY_SIZE(da850_edma_resources),
- .resource = da850_edma_resources,
+ .num_resources = ARRAY_SIZE(da850_edma1_resources),
+ .resource = da850_edma1_resources,
};
int __init da830_register_edma(struct edma_rsv_info *rsv)
{
- da830_edma_cc0_info.rsv = rsv;
+ da8xx_edma0_pdata.rsv = rsv;
- return platform_device_register(&da830_edma_device);
+ return platform_device_register(&da8xx_edma0_device);
}
int __init da850_register_edma(struct edma_rsv_info *rsv[2])
{
+ int ret;
+
if (rsv) {
- da850_edma_cc_info[0].rsv = rsv[0];
- da850_edma_cc_info[1].rsv = rsv[1];
+ da8xx_edma0_pdata.rsv = rsv[0];
+ da850_edma1_pdata.rsv = rsv[1];
}
- return platform_device_register(&da850_edma_device);
+ ret = platform_device_register(&da8xx_edma0_device);
+ if (ret) {
+ pr_warn("%s: Failed to register eDMA0\n", __func__);
+ return ret;
+ }
+ return platform_device_register(&da850_edma1_device);
}
static struct resource da8xx_i2c_resources0[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 567dc56fe8cd..a50bb9c66952 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -569,49 +569,44 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
-static s8
-queue_priority_mapping[][2] = {
+static s8 queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{1, 7},
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm355_edma_pdata = {
.queue_priority_mapping = queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -621,7 +616,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm355_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm355_edma_info,
+ .dev.platform_data = &dm355_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 6a890a8486d0..2068cbeaeb03 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -853,8 +853,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
};
/* Four Transfer Controllers on DM365 */
-static s8
-dm365_queue_priority_mapping[][2] = {
+static s8 dm365_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 7},
{1, 7},
@@ -863,53 +862,49 @@ dm365_queue_priority_mapping[][2] = {
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm365_edma_pdata = {
.queue_priority_mapping = dm365_queue_priority_mapping,
.default_queue = EVENTQ_3,
};
-static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc2",
+ .name = "edma3_tc2",
.start = 0x01c10800,
.end = 0x01c10800 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc3",
+ .name = "edma3_tc3",
.start = 0x01c10c00,
.end = 0x01c10c00 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -919,7 +914,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm365_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm365_edma_info,
+ .dev.platform_data = &dm365_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index dc52657909c4..d759ca8e58e8 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -498,49 +498,44 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
-static s8
-queue_priority_mapping[][2] = {
+static s8 queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{1, 7},
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm644x_edma_pdata = {
.queue_priority_mapping = queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -550,7 +545,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm644x_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm644x_edma_info,
+ .dev.platform_data = &dm644x_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 3f842bb266d6..219ebc8f674a 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -531,8 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
/* Four Transfer Controllers on DM646x */
-static s8
-dm646x_queue_priority_mapping[][2] = {
+static s8 dm646x_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 4},
{1, 0},
@@ -541,53 +540,49 @@ dm646x_queue_priority_mapping[][2] = {
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm646x_edma_pdata = {
.queue_priority_mapping = dm646x_queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc2",
+ .name = "edma3_tc2",
.start = 0x01c10800,
.end = 0x01c10800 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc3",
+ .name = "edma3_tc3",
.start = 0x01c10c00,
.end = 0x01c10c00 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -597,7 +592,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm646x_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm646x_edma_info,
+ .dev.platform_data = &dm646x_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
@@ -936,7 +931,7 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
int __init dm646x_init_edma(struct edma_rsv_info *rsv)
{
- edma_cc0_info.rsv = rsv;
+ dm646x_edma_pdata.rsv = rsv;
return platform_device_register(&dm646x_edma_device);
}
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 05/21] ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (3 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 04/21] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 06/21] ARM: common: edma: Internal API to use pointer to 'struct edma' Peter Ujfalusi
` (16 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
If the of_dma_controller is registered in the non dmaengine driver we could
have race condition:
the of_dma_controller has been registered, but the dmaengine driver is not
yet probed. Drivers requesting DMA channels during this window will fail
since we do not yet have dmaengine drivers registered.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 10 ----------
drivers/dma/edma.c | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 72fce68a959f..dc960de1a95f 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -29,7 +29,6 @@
#include <linux/dma-mapping.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
-#include <linux/of_dma.h>
#include <linux/of_irq.h>
#include <linux/pm_runtime.h>
@@ -1191,10 +1190,6 @@ static int edma_of_parse_dt(struct device *dev,
return ret;
}
-static struct of_dma_filter_info edma_filter_info = {
- .filter_fn = edma_filter_fn,
-};
-
static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
struct device_node *node)
{
@@ -1209,11 +1204,6 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
if (ret)
return ERR_PTR(ret);
- dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
- dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
- of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
- &edma_filter_info);
-
return info;
}
#else
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 19fa49d6f555..fcb4680efed7 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -25,6 +25,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/of.h>
+#include <linux/of_dma.h>
#include <linux/platform_data/edma.h>
@@ -987,9 +988,14 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
INIT_LIST_HEAD(&dma->channels);
}
+static struct of_dma_filter_info edma_filter_info = {
+ .filter_fn = edma_filter_fn,
+};
+
static int edma_probe(struct platform_device *pdev)
{
struct edma_cc *ecc;
+ struct device_node *parent_node = pdev->dev.parent->of_node;
int ret;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
@@ -1024,6 +1030,13 @@ static int edma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ecc);
+ if (parent_node) {
+ dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
+ dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
+ of_dma_controller_register(parent_node, of_dma_simple_xlate,
+ &edma_filter_info);
+ }
+
dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
return 0;
@@ -1037,7 +1050,10 @@ static int edma_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct edma_cc *ecc = dev_get_drvdata(dev);
+ struct device_node *parent_node = pdev->dev.parent->of_node;
+ if (parent_node)
+ of_dma_controller_free(parent_node);
dma_async_device_unregister(&ecc->dma_slave);
edma_free_slot(ecc->dummy_slot);
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 06/21] ARM: common: edma: Internal API to use pointer to 'struct edma'
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (4 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 05/21] ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 07/21] ARM/dmaengine: edma: Public API to use private struct pointer Peter Ujfalusi
` (15 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Merge the iomem into the 'struct edma' and change the internal (static)
functions to use pointer to the edma_cc instead of the ctlr number.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 400 ++++++++++++++++++++++++-------------------------
1 file changed, 197 insertions(+), 203 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index dc960de1a95f..5fd8293a48aa 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -114,108 +114,141 @@
#define EDMA_MAX_PARAMENTRY 512
/*****************************************************************************/
+struct edma {
+ struct device *dev;
+ void __iomem *base;
+
+ /* how many dma resources of each type */
+ unsigned num_channels;
+ unsigned num_region;
+ unsigned num_slots;
+ unsigned num_tc;
+ enum dma_event_q default_queue;
-static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
+ /* list of channels with no even trigger; terminated by "-1" */
+ const s8 *noevent;
+
+ struct edma_soc_info *info;
+ int id;
+
+ /* The edma_inuse bit for each PaRAM slot is clear unless the
+ * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+ */
+ DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-static inline unsigned int edma_read(unsigned ctlr, int offset)
+ /* The edma_unused bit for each channel is clear unless
+ * it is not being used on this platform. It uses a bit
+ * of SOC-specific initialization code.
+ */
+ DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
+
+ struct dma_interrupt_data {
+ void (*callback)(unsigned channel, unsigned short ch_status,
+ void *data);
+ void *data;
+ } intr_data[EDMA_MAX_DMACH];
+};
+/*****************************************************************************/
+
+static inline unsigned int edma_read(struct edma *cc, int offset)
{
- return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
+ return (unsigned int)__raw_readl(cc->base + offset);
}
-static inline void edma_write(unsigned ctlr, int offset, int val)
+static inline void edma_write(struct edma *cc, int offset, int val)
{
- __raw_writel(val, edmacc_regs_base[ctlr] + offset);
+ __raw_writel(val, cc->base + offset);
}
-static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
- unsigned or)
+static inline void edma_modify(struct edma *cc, int offset, unsigned and,
+ unsigned or)
{
- unsigned val = edma_read(ctlr, offset);
+ unsigned val = edma_read(cc, offset);
val &= and;
val |= or;
- edma_write(ctlr, offset, val);
+ edma_write(cc, offset, val);
}
-static inline void edma_and(unsigned ctlr, int offset, unsigned and)
+static inline void edma_and(struct edma *cc, int offset, unsigned and)
{
- unsigned val = edma_read(ctlr, offset);
+ unsigned val = edma_read(cc, offset);
val &= and;
- edma_write(ctlr, offset, val);
+ edma_write(cc, offset, val);
}
-static inline void edma_or(unsigned ctlr, int offset, unsigned or)
+static inline void edma_or(struct edma *cc, int offset, unsigned or)
{
- unsigned val = edma_read(ctlr, offset);
+ unsigned val = edma_read(cc, offset);
val |= or;
- edma_write(ctlr, offset, val);
+ edma_write(cc, offset, val);
}
-static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
+static inline unsigned int edma_read_array(struct edma *cc, int offset, int i)
{
- return edma_read(ctlr, offset + (i << 2));
+ return edma_read(cc, offset + (i << 2));
}
-static inline void edma_write_array(unsigned ctlr, int offset, int i,
+static inline void edma_write_array(struct edma *cc, int offset, int i,
unsigned val)
{
- edma_write(ctlr, offset + (i << 2), val);
+ edma_write(cc, offset + (i << 2), val);
}
-static inline void edma_modify_array(unsigned ctlr, int offset, int i,
+static inline void edma_modify_array(struct edma *cc, int offset, int i,
unsigned and, unsigned or)
{
- edma_modify(ctlr, offset + (i << 2), and, or);
+ edma_modify(cc, offset + (i << 2), and, or);
}
-static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
+static inline void edma_or_array(struct edma *cc, int offset, int i, unsigned or)
{
- edma_or(ctlr, offset + (i << 2), or);
+ edma_or(cc, offset + (i << 2), or);
}
-static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
+static inline void edma_or_array2(struct edma *cc, int offset, int i, int j,
unsigned or)
{
- edma_or(ctlr, offset + ((i*2 + j) << 2), or);
+ edma_or(cc, offset + ((i*2 + j) << 2), or);
}
-static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
+static inline void edma_write_array2(struct edma *cc, int offset, int i, int j,
unsigned val)
{
- edma_write(ctlr, offset + ((i*2 + j) << 2), val);
+ edma_write(cc, offset + ((i*2 + j) << 2), val);
}
-static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
+static inline unsigned int edma_shadow0_read(struct edma *cc, int offset)
{
- return edma_read(ctlr, EDMA_SHADOW0 + offset);
+ return edma_read(cc, EDMA_SHADOW0 + offset);
}
-static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
+static inline unsigned int edma_shadow0_read_array(struct edma *cc, int offset,
int i)
{
- return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
+ return edma_read(cc, EDMA_SHADOW0 + offset + (i << 2));
}
-static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
+static inline void edma_shadow0_write(struct edma *cc, int offset, unsigned val)
{
- edma_write(ctlr, EDMA_SHADOW0 + offset, val);
+ edma_write(cc, EDMA_SHADOW0 + offset, val);
}
-static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
+static inline void edma_shadow0_write_array(struct edma *cc, int offset, int i,
unsigned val)
{
- edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
+ edma_write(cc, EDMA_SHADOW0 + offset + (i << 2), val);
}
-static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
+static inline unsigned int edma_parm_read(struct edma *cc, int offset,
int param_no)
{
- return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
+ return edma_read(cc, EDMA_PARM + offset + (param_no << 5));
}
-static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_write(struct edma *cc, int offset, int param_no,
unsigned val)
{
- edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
+ edma_write(cc, EDMA_PARM + offset + (param_no << 5), val);
}
-static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_modify(struct edma *cc, int offset, int param_no,
unsigned and, unsigned or)
{
- edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
+ edma_modify(cc, EDMA_PARM + offset + (param_no << 5), and, or);
}
-static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_and(struct edma *cc, int offset, int param_no,
unsigned and)
{
- edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
+ edma_and(cc, EDMA_PARM + offset + (param_no << 5), and);
}
-static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_or(struct edma *cc, int offset, int param_no,
unsigned or)
{
- edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
+ edma_or(cc, EDMA_PARM + offset + (param_no << 5), or);
}
static inline void set_bits(int offset, int len, unsigned long *p)
@@ -231,41 +264,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
}
/*****************************************************************************/
-
-/* actual number of DMA channels and slots on this silicon */
-struct edma {
- struct device *dev;
- /* how many dma resources of each type */
- unsigned num_channels;
- unsigned num_region;
- unsigned num_slots;
- unsigned num_tc;
- enum dma_event_q default_queue;
-
- /* list of channels with no even trigger; terminated by "-1" */
- const s8 *noevent;
-
- struct edma_soc_info *info;
- int id;
-
- /* The edma_inuse bit for each PaRAM slot is clear unless the
- * channel is in use ... by ARM or DSP, for QDMA, or whatever.
- */
- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-
- /* The edma_unused bit for each channel is clear unless
- * it is not being used on this platform. It uses a bit
- * of SOC-specific initialization code.
- */
- DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
-
- struct dma_interrupt_data {
- void (*callback)(unsigned channel, unsigned short ch_status,
- void *data);
- void *data;
- } intr_data[EDMA_MAX_DMACH];
-};
-
static struct edma *edma_cc[EDMA_MAX_CC];
static int arch_num_cc;
@@ -282,26 +280,25 @@ static const struct of_device_id edma_of_ids[] = {
/*****************************************************************************/
-static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
- enum dma_event_q queue_no)
+static void map_dmach_queue(struct edma *cc, unsigned ch_no,
+ enum dma_event_q queue_no)
{
int bit = (ch_no & 0x7) * 4;
/* default to low priority queue */
if (queue_no == EVENTQ_DEFAULT)
- queue_no = edma_cc[ctlr]->default_queue;
+ queue_no = cc->default_queue;
queue_no &= 7;
- edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
- ~(0x7 << bit), queue_no << bit);
+ edma_modify_array(cc, EDMA_DMAQNUM, (ch_no >> 3),
+ ~(0x7 << bit), queue_no << bit);
}
-static void assign_priority_to_queue(unsigned ctlr, int queue_no,
- int priority)
+static void assign_priority_to_queue(struct edma *cc, int queue_no,
+ int priority)
{
int bit = queue_no * 4;
- edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
- ((priority & 0x7) << bit));
+ edma_modify(cc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
}
/**
@@ -315,35 +312,30 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no,
* included in that particular EDMA variant (Eg : dm646x)
*
*/
-static void map_dmach_param(unsigned ctlr)
+static void map_dmach_param(struct edma *cc)
{
int i;
for (i = 0; i < EDMA_MAX_DMACH; i++)
- edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
+ edma_write_array(cc, EDMA_DCHMAP , i , (i << 5));
}
-static inline void
-setup_dma_interrupt(unsigned lch,
+static inline void setup_dma_interrupt(struct edma *cc, unsigned lch,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(lch);
lch = EDMA_CHAN_SLOT(lch);
if (!callback)
- edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
- BIT(lch & 0x1f));
+ edma_shadow0_write_array(cc, SH_IECR, lch >> 5,
+ BIT(lch & 0x1f));
- edma_cc[ctlr]->intr_data[lch].callback = callback;
- edma_cc[ctlr]->intr_data[lch].data = data;
+ cc->intr_data[lch].callback = callback;
+ cc->intr_data[lch].data = data;
if (callback) {
- edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
- BIT(lch & 0x1f));
- edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
- BIT(lch & 0x1f));
+ edma_shadow0_write_array(cc, SH_ICR, lch >> 5, BIT(lch & 0x1f));
+ edma_shadow0_write_array(cc, SH_IESR, lch >> 5,
+ BIT(lch & 0x1f));
}
}
@@ -366,15 +358,15 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
dev_dbg(cc->dev, "dma_irq_handler\n");
- sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
+ sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 0);
if (!sh_ipr) {
- sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
+ sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 1);
if (!sh_ipr)
return IRQ_NONE;
- sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
+ sh_ier = edma_shadow0_read_array(cc, SH_IER, 1);
bank = 1;
} else {
- sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
+ sh_ier = edma_shadow0_read_array(cc, SH_IER, 0);
bank = 0;
}
@@ -390,8 +382,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
if (sh_ier & BIT(slot)) {
channel = (bank << 5) | slot;
/* Clear the corresponding IPR bits */
- edma_shadow0_write_array(ctlr, SH_ICR, bank,
- BIT(slot));
+ edma_shadow0_write_array(cc, SH_ICR, bank, BIT(slot));
if (cc->intr_data[channel].callback)
cc->intr_data[channel].callback(
EDMA_CTLR_CHAN(ctlr, channel),
@@ -400,7 +391,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
}
} while (sh_ipr);
- edma_shadow0_write(ctlr, SH_IEVAL, 1);
+ edma_shadow0_write(cc, SH_IEVAL, 1);
return IRQ_HANDLED;
}
@@ -422,30 +413,30 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
dev_dbg(cc->dev, "dma_ccerr_handler\n");
- if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- (edma_read(ctlr, EDMA_QEMR) == 0) &&
- (edma_read(ctlr, EDMA_CCERR) == 0))
+ if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(cc, EDMA_EMR, 1) == 0) &&
+ (edma_read(cc, EDMA_QEMR) == 0) &&
+ (edma_read(cc, EDMA_CCERR) == 0))
return IRQ_NONE;
while (1) {
int j = -1;
- if (edma_read_array(ctlr, EDMA_EMR, 0))
+ if (edma_read_array(cc, EDMA_EMR, 0))
j = 0;
- else if (edma_read_array(ctlr, EDMA_EMR, 1))
+ else if (edma_read_array(cc, EDMA_EMR, 1))
j = 1;
if (j >= 0) {
dev_dbg(cc->dev, "EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
+ edma_read_array(cc, EDMA_EMR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
- if (edma_read_array(ctlr, EDMA_EMR, j) &
+ if (edma_read_array(cc, EDMA_EMR, j) &
BIT(i)) {
/* Clear the corresponding EMR bits */
- edma_write_array(ctlr, EDMA_EMCR, j,
- BIT(i));
+ edma_write_array(cc, EDMA_EMCR, j,
+ BIT(i));
/* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR,
+ edma_shadow0_write_array(cc, SH_SECR,
j, BIT(i));
if (cc->intr_data[k].callback) {
cc->intr_data[k].callback(
@@ -455,44 +446,44 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
}
}
}
- } else if (edma_read(ctlr, EDMA_QEMR)) {
+ } else if (edma_read(cc, EDMA_QEMR)) {
dev_dbg(cc->dev, "QEMR %02x\n",
- edma_read(ctlr, EDMA_QEMR));
+ edma_read(cc, EDMA_QEMR));
for (i = 0; i < 8; i++) {
- if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
+ if (edma_read(cc, EDMA_QEMR) & BIT(i)) {
/* Clear the corresponding IPR bits */
- edma_write(ctlr, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ctlr, SH_QSECR,
- BIT(i));
+ edma_write(cc, EDMA_QEMCR, BIT(i));
+ edma_shadow0_write(cc, SH_QSECR,
+ BIT(i));
/* NOTE: not reported!! */
}
}
- } else if (edma_read(ctlr, EDMA_CCERR)) {
+ } else if (edma_read(cc, EDMA_CCERR)) {
dev_dbg(cc->dev, "CCERR %08x\n",
- edma_read(ctlr, EDMA_CCERR));
+ edma_read(cc, EDMA_CCERR));
/* FIXME: CCERR.BIT(16) ignored! much better
* to just write CCERRCLR with CCERR value...
*/
for (i = 0; i < 8; i++) {
- if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
+ if (edma_read(cc, EDMA_CCERR) & BIT(i)) {
/* Clear the corresponding IPR bits */
- edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
+ edma_write(cc, EDMA_CCERRCLR, BIT(i));
/* NOTE: not reported!! */
}
}
}
- if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- (edma_read(ctlr, EDMA_QEMR) == 0) &&
- (edma_read(ctlr, EDMA_CCERR) == 0))
+ if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(cc, EDMA_EMR, 1) == 0) &&
+ (edma_read(cc, EDMA_QEMR) == 0) &&
+ (edma_read(cc, EDMA_CCERR) == 0))
break;
cnt++;
if (cnt > 10)
break;
}
- edma_write(ctlr, EDMA_EEVAL, 1);
+ edma_write(cc, EDMA_EEVAL, 1);
return IRQ_HANDLED;
}
@@ -629,18 +620,19 @@ int edma_alloc_channel(int channel,
}
/* ensure access through shadow region 0 */
- edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+ edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
/* ensure no events are pending */
edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ PARM_SIZE);
if (callback)
- setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
- callback, data);
+ setup_dma_interrupt(edma_cc[ctlr],
+ EDMA_CTLR_CHAN(ctlr, channel), callback,
+ data);
- map_dmach_queue(ctlr, channel, eventq_no);
+ map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
return EDMA_CTLR_CHAN(ctlr, channel);
}
@@ -668,11 +660,11 @@ void edma_free_channel(unsigned channel)
if (channel >= edma_cc[ctlr]->num_channels)
return;
- setup_dma_interrupt(channel, NULL, NULL);
+ setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL);
/* REVISIT should probably take out of shadow region 0 */
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ PARM_SIZE);
clear_bit(channel, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@@ -716,8 +708,8 @@ int edma_alloc_slot(unsigned ctlr, int slot)
return -EBUSY;
}
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
+ PARM_SIZE);
return EDMA_CTLR_CHAN(ctlr, slot);
}
@@ -742,8 +734,8 @@ void edma_free_slot(unsigned slot)
slot >= edma_cc[ctlr]->num_slots)
return;
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
+ PARM_SIZE);
clear_bit(slot, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@@ -768,7 +760,7 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
offs = PARM_OFFSET(slot);
offs += dst ? PARM_DST : PARM_SRC;
- return edma_read(ctlr, offs);
+ return edma_read(edma_cc[ctlr], offs);
}
/**
@@ -791,7 +783,7 @@ void edma_link(unsigned from, unsigned to)
return;
if (to >= edma_cc[ctlr_to]->num_slots)
return;
- edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000,
PARM_OFFSET(to));
}
EXPORT_SYMBOL(edma_link);
@@ -819,8 +811,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
if (slot >= edma_cc[ctlr]->num_slots)
return;
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
- PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE);
}
EXPORT_SYMBOL(edma_write_slot);
@@ -841,8 +832,8 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
if (slot >= edma_cc[ctlr]->num_slots)
return;
- memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- PARM_SIZE);
+ memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot),
+ PARM_SIZE);
}
EXPORT_SYMBOL(edma_read_slot);
@@ -867,7 +858,8 @@ void edma_pause(unsigned channel)
if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
+ edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5,
+ mask);
}
}
EXPORT_SYMBOL(edma_pause);
@@ -888,7 +880,8 @@ void edma_resume(unsigned channel)
if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
+ edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5,
+ mask);
}
}
EXPORT_SYMBOL(edma_resume);
@@ -902,10 +895,11 @@ int edma_trigger_channel(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
+ edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask);
pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
+ edma_shadow0_read_array(edma_cc[ctlr], SH_ESR,
+ (channel >> 5)));
return 0;
}
EXPORT_SYMBOL(edma_trigger_channel);
@@ -929,28 +923,29 @@ int edma_start(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_cc[ctlr]->num_channels) {
+ struct edma *cc = edma_cc[ctlr];
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
/* EDMA channels without event association */
- if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
+ if (test_bit(channel, cc->edma_unused)) {
pr_debug("EDMA: ESR%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_ESR, j));
- edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
+ edma_shadow0_read_array(cc, SH_ESR, j));
+ edma_shadow0_write_array(cc, SH_ESR, j, mask);
return 0;
}
/* EDMA channel with event association */
pr_debug("EDMA: ER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_ER, j));
+ edma_shadow0_read_array(cc, SH_ER, j));
/* Clear any pending event or error */
- edma_write_array(ctlr, EDMA_ECR, j, mask);
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ edma_write_array(cc, EDMA_ECR, j, mask);
+ edma_write_array(cc, EDMA_EMCR, j, mask);
/* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
+ edma_shadow0_write_array(cc, SH_SECR, j, mask);
+ edma_shadow0_write_array(cc, SH_EESR, j, mask);
pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_EER, j));
+ edma_shadow0_read_array(cc, SH_EER, j));
return 0;
}
@@ -975,19 +970,20 @@ void edma_stop(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_cc[ctlr]->num_channels) {
+ struct edma *cc = edma_cc[ctlr];
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ edma_shadow0_write_array(cc, SH_EECR, j, mask);
+ edma_shadow0_write_array(cc, SH_ECR, j, mask);
+ edma_shadow0_write_array(cc, SH_SECR, j, mask);
+ edma_write_array(cc, EDMA_EMCR, j, mask);
/* clear possibly pending completion interrupt */
- edma_shadow0_write_array(ctlr, SH_ICR, j, mask);
+ edma_shadow0_write_array(cc, SH_ICR, j, mask);
pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_EER, j));
+ edma_shadow0_read_array(cc, SH_EER, j));
/* REVISIT: consider guarding against inappropriate event
* chaining by overwriting with dummy_paramset.
@@ -1017,17 +1013,18 @@ void edma_clean_channel(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_cc[ctlr]->num_channels) {
+ struct edma *cc = edma_cc[ctlr];
int j = (channel >> 5);
unsigned int mask = BIT(channel & 0x1f);
pr_debug("EDMA: EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
- edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ edma_read_array(cc, EDMA_EMR, j));
+ edma_shadow0_write_array(cc, SH_ECR, j, mask);
/* Clear the corresponding EMR bits */
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ edma_write_array(cc, EDMA_EMCR, j, mask);
/* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
+ edma_shadow0_write_array(cc, SH_SECR, j, mask);
+ edma_write(cc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
}
}
EXPORT_SYMBOL(edma_clean_channel);
@@ -1056,7 +1053,7 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
if (eventq_no >= edma_cc[ctlr]->num_tc)
return;
- map_dmach_queue(ctlr, channel, eventq_no);
+ map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
}
EXPORT_SYMBOL(edma_assign_channel_eventq);
@@ -1068,7 +1065,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
s8 (*queue_priority_map)[2];
/* Decode the eDMA3 configuration from CCCFG register */
- cccfg = edma_read(cc_id, EDMA_CCCFG);
+ cccfg = edma_read(edma_cc, EDMA_CCCFG);
value = GET_NUM_REGN(cccfg);
edma_cc->num_region = BIT(value);
@@ -1281,10 +1278,6 @@ static int edma_probe(struct platform_device *pdev)
}
}
- edmacc_regs_base[dev_id] = devm_ioremap_resource(dev, mem);
- if (IS_ERR(edmacc_regs_base[dev_id]))
- return PTR_ERR(edmacc_regs_base[dev_id]);
-
edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
if (!edma_cc[dev_id])
return -ENOMEM;
@@ -1294,6 +1287,10 @@ static int edma_probe(struct platform_device *pdev)
cc->id = dev_id;
dev_set_drvdata(dev, cc);
+ cc->base = devm_ioremap_resource(dev, mem);
+ if (IS_ERR(cc->base))
+ return PTR_ERR(cc->base);
+
/* Get eDMA3 configuration from IP */
ret = edma_setup_from_hw(dev, info, cc, dev_id);
if (ret)
@@ -1301,11 +1298,9 @@ static int edma_probe(struct platform_device *pdev)
cc->default_queue = info->default_queue;
- dev_dbg(dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[dev_id]);
-
for (i = 0; i < cc->num_slots; i++)
- memcpy_toio(edmacc_regs_base[dev_id] + PARM_OFFSET(i),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(i), &dummy_paramset,
+ PARM_SIZE);
/* Mark all channels as unused */
memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused));
@@ -1374,23 +1369,23 @@ static int edma_probe(struct platform_device *pdev)
}
for (i = 0; i < cc->num_channels; i++)
- map_dmach_queue(dev_id, i, info->default_queue);
+ map_dmach_queue(cc, i, info->default_queue);
queue_priority_mapping = info->queue_priority_mapping;
/* Event queue priority mapping */
for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(dev_id, queue_priority_mapping[i][0],
+ assign_priority_to_queue(cc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
/* Map the channel to param entry if channel mapping logic exist */
- if (edma_read(dev_id, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(dev_id);
+ if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(cc);
for (i = 0; i < cc->num_region; i++) {
- edma_write_array2(dev_id, EDMA_DRAE, i, 0, 0x0);
- edma_write_array2(dev_id, EDMA_DRAE, i, 1, 0x0);
- edma_write_array(dev_id, EDMA_QRAE, i, 0x0);
+ edma_write_array2(cc, EDMA_DRAE, i, 0, 0x0);
+ edma_write_array2(cc, EDMA_DRAE, i, 1, 0x0);
+ edma_write_array(cc, EDMA_QRAE, i, 0x0);
}
cc->info = info;
arch_num_cc++;
@@ -1413,20 +1408,19 @@ static int edma_pm_resume(struct device *dev)
/* Event queue priority mapping */
for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(cc->id, queue_priority_mapping[i][0],
+ assign_priority_to_queue(cc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
/* Map the channel to param entry if channel mapping logic */
- if (edma_read(cc->id, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(cc->id);
+ if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(cc);
for (i = 0; i < cc->num_channels; i++) {
if (test_bit(i, cc->edma_inuse)) {
/* ensure access through shadow region 0 */
- edma_or_array2(cc->id, EDMA_DRAE, 0, i >> 5,
- BIT(i & 0x1f));
+ edma_or_array2(cc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f));
- setup_dma_interrupt(EDMA_CTLR_CHAN(cc->id, i),
+ setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, i),
cc->intr_data[i].callback,
cc->intr_data[i].data);
}
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 07/21] ARM/dmaengine: edma: Public API to use private struct pointer
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (5 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 06/21] ARM: common: edma: Internal API to use pointer to 'struct edma' Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 08/21] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Peter Ujfalusi
` (14 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Instead of relying on indexes pointing to edma private date in the global
pointer array, pass the private data pointer via the public API.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 305 ++++++++++++++++++-------------------
drivers/dma/edma.c | 79 +++++-----
include/linux/platform_data/edma.h | 38 +++--
3 files changed, 214 insertions(+), 208 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 5fd8293a48aa..15b68ce98ec7 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -130,7 +130,7 @@ struct edma {
struct edma_soc_info *info;
int id;
-
+ bool unused_chan_list_done;
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
@@ -264,7 +264,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
}
/*****************************************************************************/
-static struct edma *edma_cc[EDMA_MAX_CC];
static int arch_num_cc;
/* dummy param set used to (re)initialize parameter RAM slots */
@@ -490,14 +489,18 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
- int i, count, ctlr;
+ struct edma *cc = data;
+ int i, count;
struct of_phandle_args dma_spec;
if (dev->of_node) {
+ struct platform_device *dma_pdev;
+
count = of_property_count_strings(dev->of_node, "dma-names");
if (count < 0)
return 0;
for (i = 0; i < count; i++) {
+
if (of_parse_phandle_with_args(dev->of_node, "dmas",
"#dma-cells", i,
&dma_spec))
@@ -508,8 +511,12 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
continue;
}
+ dma_pdev = of_find_device_by_node(dma_spec.np);
+ if (&dma_pdev->dev != cc->dev)
+ continue;
+
clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
- edma_cc[0]->edma_unused);
+ cc->edma_unused);
of_node_put(dma_spec.np);
}
return 0;
@@ -517,11 +524,11 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/* For non-OF case */
for (i = 0; i < pdev->num_resources; i++) {
- if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
- (int)pdev->resource[i].start >= 0) {
- ctlr = EDMA_CTLR(pdev->resource[i].start);
+ struct resource *res = &pdev->resource[i];
+
+ if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
- edma_cc[ctlr]->edma_unused);
+ cc->edma_unused);
}
}
@@ -530,8 +537,6 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/*-----------------------------------------------------------------------*/
-static bool unused_chan_list_done;
-
/* Resource alloc/free: dma channels, parameter RAM slots */
/**
@@ -564,77 +569,73 @@ static bool unused_chan_list_done;
*
* Returns the number of the channel, else negative errno.
*/
-int edma_alloc_channel(int channel,
+int edma_alloc_channel(struct edma *cc, int channel,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data,
enum dma_event_q eventq_no)
{
- unsigned i, done = 0, ctlr = 0;
+ unsigned done = 0;
int ret = 0;
- if (!unused_chan_list_done) {
+ if (!cc->unused_chan_list_done) {
/*
* Scan all the platform devices to find out the EDMA channels
* used and clear them in the unused list, making the rest
* available for ARM usage.
*/
- ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
- prepare_unused_channel_list);
+ ret = bus_for_each_dev(&platform_bus_type, NULL, cc,
+ prepare_unused_channel_list);
if (ret < 0)
return ret;
- unused_chan_list_done = true;
+ cc->unused_chan_list_done = true;
}
if (channel >= 0) {
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n",
+ __func__, cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
}
if (channel < 0) {
- for (i = 0; i < arch_num_cc; i++) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(edma_cc[i]->edma_unused,
- edma_cc[i]->num_channels,
- channel);
- if (channel == edma_cc[i]->num_channels)
- break;
- if (!test_and_set_bit(channel,
- edma_cc[i]->edma_inuse)) {
- done = 1;
- ctlr = i;
- break;
- }
- channel++;
- }
- if (done)
+ channel = 0;
+ for (;;) {
+ channel = find_next_bit(cc->edma_unused,
+ cc->num_channels, channel);
+ if (channel == cc->num_channels)
+ break;
+ if (!test_and_set_bit(channel, cc->edma_inuse)) {
+ done = 1;
break;
+ }
+ channel++;
}
if (!done)
return -ENOMEM;
- } else if (channel >= edma_cc[ctlr]->num_channels) {
+ } else if (channel >= cc->num_channels) {
return -EINVAL;
- } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(channel, cc->edma_inuse)) {
return -EBUSY;
}
/* ensure access through shadow region 0 */
- edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+ edma_or_array2(cc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
/* ensure no events are pending */
- edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ edma_stop(cc, EDMA_CTLR_CHAN(cc->id, channel));
+ memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
PARM_SIZE);
if (callback)
- setup_dma_interrupt(edma_cc[ctlr],
- EDMA_CTLR_CHAN(ctlr, channel), callback,
- data);
+ setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, channel),
+ callback, data);
- map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
+ map_dmach_queue(cc, channel, eventq_no);
- return EDMA_CTLR_CHAN(ctlr, channel);
+ return EDMA_CTLR_CHAN(cc->id, channel);
}
EXPORT_SYMBOL(edma_alloc_channel);
@@ -650,22 +651,25 @@ EXPORT_SYMBOL(edma_alloc_channel);
* will not be reactivated by linking, chaining, or software calls to
* edma_start().
*/
-void edma_free_channel(unsigned channel)
+void edma_free_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_cc[ctlr]->num_channels)
+ if (channel >= cc->num_channels)
return;
- setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL);
+ setup_dma_interrupt(cc, channel, NULL, NULL);
/* REVISIT should probably take out of shadow region 0 */
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
PARM_SIZE);
- clear_bit(channel, edma_cc[ctlr]->edma_inuse);
+ clear_bit(channel, cc->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@@ -683,35 +687,29 @@ EXPORT_SYMBOL(edma_free_channel);
*
* Returns the number of the slot, else negative errno.
*/
-int edma_alloc_slot(unsigned ctlr, int slot)
+int edma_alloc_slot(struct edma *cc, int slot)
{
- if (!edma_cc[ctlr])
- return -EINVAL;
-
- if (slot >= 0)
+ if (slot > 0)
slot = EDMA_CHAN_SLOT(slot);
-
if (slot < 0) {
- slot = edma_cc[ctlr]->num_channels;
+ slot = cc->num_channels;
for (;;) {
- slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
- edma_cc[ctlr]->num_slots, slot);
- if (slot == edma_cc[ctlr]->num_slots)
+ slot = find_next_zero_bit(cc->edma_inuse, cc->num_slots,
+ slot);
+ if (slot == cc->num_slots)
return -ENOMEM;
- if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
+ if (!test_and_set_bit(slot, cc->edma_inuse))
break;
}
- } else if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots) {
+ } else if (slot < cc->num_channels || slot >= cc->num_slots) {
return -EINVAL;
- } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(slot, cc->edma_inuse)) {
return -EBUSY;
}
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
- PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
- return EDMA_CTLR_CHAN(ctlr, slot);
+ return slot;
}
EXPORT_SYMBOL(edma_alloc_slot);
@@ -723,20 +721,15 @@ EXPORT_SYMBOL(edma_alloc_slot);
* Callers are responsible for ensuring the slot is inactive, and will
* not be activated.
*/
-void edma_free_slot(unsigned slot)
+void edma_free_slot(struct edma *cc, unsigned slot)
{
- unsigned ctlr;
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots)
+ if (slot < cc->num_channels || slot >= cc->num_slots)
return;
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
- PARM_SIZE);
- clear_bit(slot, edma_cc[ctlr]->edma_inuse);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
+ clear_bit(slot, cc->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@@ -751,16 +744,15 @@ EXPORT_SYMBOL(edma_free_slot);
*
* Returns the position of the current active slot
*/
-dma_addr_t edma_get_position(unsigned slot, bool dst)
+dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst)
{
- u32 offs, ctlr = EDMA_CTLR(slot);
+ u32 offs;
slot = EDMA_CHAN_SLOT(slot);
-
offs = PARM_OFFSET(slot);
offs += dst ? PARM_DST : PARM_SRC;
- return edma_read(edma_cc[ctlr], offs);
+ return edma_read(cc, offs);
}
/**
@@ -770,21 +762,15 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
*
* The originating slot should not be part of any active DMA transfer.
*/
-void edma_link(unsigned from, unsigned to)
+void edma_link(struct edma *cc, unsigned from, unsigned to)
{
- unsigned ctlr_from, ctlr_to;
-
- ctlr_from = EDMA_CTLR(from);
from = EDMA_CHAN_SLOT(from);
- ctlr_to = EDMA_CTLR(to);
to = EDMA_CHAN_SLOT(to);
-
- if (from >= edma_cc[ctlr_from]->num_slots)
+ if (from >= cc->num_slots || to >= cc->num_slots)
return;
- if (to >= edma_cc[ctlr_to]->num_slots)
- return;
- edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000,
- PARM_OFFSET(to));
+
+ edma_parm_modify(cc, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ PARM_OFFSET(to));
}
EXPORT_SYMBOL(edma_link);
@@ -802,16 +788,13 @@ EXPORT_SYMBOL(edma_link);
* calls to set up those parameters in small pieces, and provides
* complete control over all transfer options.
*/
-void edma_write_slot(unsigned slot, const struct edmacc_param *param)
+void edma_write_slot(struct edma *cc, unsigned slot,
+ const struct edmacc_param *param)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
+ if (slot >= cc->num_slots)
return;
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), param, PARM_SIZE);
}
EXPORT_SYMBOL(edma_write_slot);
@@ -823,17 +806,12 @@ EXPORT_SYMBOL(edma_write_slot);
* Use this to read data from a parameter RAM slot, perhaps to
* save them as a template for later reuse.
*/
-void edma_read_slot(unsigned slot, struct edmacc_param *param)
+void edma_read_slot(struct edma *cc, unsigned slot, struct edmacc_param *param)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
+ if (slot >= cc->num_slots)
return;
- memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot),
- PARM_SIZE);
+ memcpy_fromio(param, cc->base + PARM_OFFSET(slot), PARM_SIZE);
}
EXPORT_SYMBOL(edma_read_slot);
@@ -848,18 +826,19 @@ EXPORT_SYMBOL(edma_read_slot);
* This temporarily disables EDMA hardware events on the specified channel,
* preventing them from triggering new transfers on its behalf
*/
-void edma_pause(unsigned channel)
+void edma_pause(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
+ if (channel < cc->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5,
- mask);
+ edma_shadow0_write_array(cc, SH_EECR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_pause);
@@ -870,36 +849,39 @@ EXPORT_SYMBOL(edma_pause);
*
* This re-enables EDMA hardware events on the specified channel.
*/
-void edma_resume(unsigned channel)
+void edma_resume(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
+ if (channel < cc->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5,
- mask);
+ edma_shadow0_write_array(cc, SH_EESR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_resume);
-int edma_trigger_channel(unsigned channel)
+int edma_trigger_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
unsigned int mask;
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask);
+ edma_shadow0_write_array(cc, SH_ESR, (channel >> 5), mask);
pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(edma_cc[ctlr], SH_ESR,
- (channel >> 5)));
+ edma_shadow0_read_array(cc, SH_ESR, (channel >> 5)));
return 0;
}
EXPORT_SYMBOL(edma_trigger_channel);
@@ -915,15 +897,16 @@ EXPORT_SYMBOL(edma_trigger_channel);
*
* Returns zero on success, else negative errno.
*/
-int edma_start(unsigned channel)
+int edma_start(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
@@ -962,15 +945,16 @@ EXPORT_SYMBOL(edma_start);
* may not be resumed, and the channel's Parameter RAM should be
* reinitialized before being reused.
*/
-void edma_stop(unsigned channel)
+void edma_stop(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
@@ -1005,15 +989,16 @@ EXPORT_SYMBOL(edma_stop);
*
*****************************************************************************/
-void edma_clean_channel(unsigned channel)
+void edma_clean_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = (channel >> 5);
unsigned int mask = BIT(channel & 0x1f);
@@ -1037,26 +1022,35 @@ EXPORT_SYMBOL(edma_clean_channel);
*
* Can be used to move a channel to a selected event queue.
*/
-void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
+void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
+ enum dma_event_q eventq_no)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_cc[ctlr]->num_channels)
+ if (channel >= cc->num_channels)
return;
/* default to low priority queue */
if (eventq_no == EVENTQ_DEFAULT)
- eventq_no = edma_cc[ctlr]->default_queue;
- if (eventq_no >= edma_cc[ctlr]->num_tc)
+ eventq_no = cc->default_queue;
+ if (eventq_no >= cc->num_tc)
return;
- map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
+ map_dmach_queue(cc, channel, eventq_no);
}
EXPORT_SYMBOL(edma_assign_channel_eventq);
+struct edma *edma_get_data(struct device *edma_dev)
+{
+ return dev_get_drvdata(edma_dev);
+}
+
+
static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
struct edma *edma_cc, int cc_id)
{
@@ -1278,11 +1272,10 @@ static int edma_probe(struct platform_device *pdev)
}
}
- edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
- if (!edma_cc[dev_id])
+ cc = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
+ if (!cc)
return -ENOMEM;
- cc = edma_cc[dev_id];
cc->dev = dev;
cc->id = dev_id;
dev_set_drvdata(dev, cc);
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index fcb4680efed7..53d48b2a700d 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -119,6 +119,7 @@ struct edma_chan {
};
struct edma_cc {
+ struct edma *cc;
int ctlr;
struct dma_device dma_slave;
struct edma_chan slave_chans[EDMA_CHANS];
@@ -150,6 +151,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc)
/* Dispatch a queued descriptor to the controller (caller holds lock) */
static void edma_execute(struct edma_chan *echan)
{
+ struct edma *cc = echan->ecc->cc;
struct virt_dma_desc *vdesc;
struct edma_desc *edesc;
struct device *dev = echan->vchan.chan.device->dev;
@@ -174,7 +176,7 @@ static void edma_execute(struct edma_chan *echan)
/* Write descriptor PaRAM set(s) */
for (i = 0; i < nslots; i++) {
j = i + edesc->processed;
- edma_write_slot(echan->slot[i], &edesc->pset[j].param);
+ edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param);
edesc->sg_len += edesc->pset[j].len;
dev_vdbg(echan->vchan.chan.device->dev,
"\n pset[%d]:\n"
@@ -199,7 +201,7 @@ static void edma_execute(struct edma_chan *echan)
edesc->pset[j].param.link_bcntrld);
/* Link to the previous slot if not the last set */
if (i != (nslots - 1))
- edma_link(echan->slot[i], echan->slot[i+1]);
+ edma_link(cc, echan->slot[i], echan->slot[i+1]);
}
edesc->processed += nslots;
@@ -211,9 +213,9 @@ static void edma_execute(struct edma_chan *echan)
*/
if (edesc->processed == edesc->pset_nr) {
if (edesc->cyclic)
- edma_link(echan->slot[nslots-1], echan->slot[1]);
+ edma_link(cc, echan->slot[nslots-1], echan->slot[1]);
else
- edma_link(echan->slot[nslots-1],
+ edma_link(cc, echan->slot[nslots-1],
echan->ecc->dummy_slot);
}
@@ -224,19 +226,19 @@ static void edma_execute(struct edma_chan *echan)
* transfers of MAX_NR_SG
*/
dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
- edma_clean_channel(echan->ch_num);
- edma_stop(echan->ch_num);
- edma_start(echan->ch_num);
- edma_trigger_channel(echan->ch_num);
+ edma_clean_channel(cc, echan->ch_num);
+ edma_stop(cc, echan->ch_num);
+ edma_start(cc, echan->ch_num);
+ edma_trigger_channel(cc, echan->ch_num);
echan->missed = 0;
} else if (edesc->processed <= MAX_NR_SG) {
dev_dbg(dev, "first transfer starting on channel %d\n",
echan->ch_num);
- edma_start(echan->ch_num);
+ edma_start(cc, echan->ch_num);
} else {
dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
echan->ch_num, edesc->processed);
- edma_resume(echan->ch_num);
+ edma_resume(cc, echan->ch_num);
}
}
@@ -254,10 +256,11 @@ static int edma_terminate_all(struct dma_chan *chan)
* echan->edesc is NULL and exit.)
*/
if (echan->edesc) {
- edma_stop(echan->ch_num);
+ edma_stop(echan->ecc->cc, echan->ch_num);
/* Move the cyclic channel back to default queue */
if (echan->edesc->cyclic)
- edma_assign_channel_eventq(echan->ch_num,
+ edma_assign_channel_eventq(echan->ecc->cc,
+ echan->ch_num,
EVENTQ_DEFAULT);
/*
* free the running request descriptor
@@ -295,7 +298,7 @@ static int edma_dma_pause(struct dma_chan *chan)
if (!echan->edesc)
return -EINVAL;
- edma_pause(echan->ch_num);
+ edma_pause(echan->ecc->cc, echan->ch_num);
return 0;
}
@@ -303,7 +306,7 @@ static int edma_dma_resume(struct dma_chan *chan)
{
struct edma_chan *echan = to_edma_chan(chan);
- edma_resume(echan->ch_num);
+ edma_resume(echan->ecc->cc, echan->ch_num);
return 0;
}
@@ -485,8 +488,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
for (i = 0; i < nslots; i++) {
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(EDMA_CTLR(echan->ch_num),
- EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -641,8 +643,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
/* Allocate a PaRAM slot, if needed */
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(EDMA_CTLR(echan->ch_num),
- EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -703,7 +704,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
}
/* Place the cyclic channel to highest priority queue */
- edma_assign_channel_eventq(echan->ch_num, EVENTQ_0);
+ edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0);
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}
@@ -711,6 +712,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
{
struct edma_chan *echan = data;
+ struct edma *cc = echan->ecc->cc;
struct device *dev = echan->vchan.chan.device->dev;
struct edma_desc *edesc;
struct edmacc_param p;
@@ -727,13 +729,13 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
} else if (edesc->processed == edesc->pset_nr) {
dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
edesc->residue = 0;
- edma_stop(echan->ch_num);
+ edma_stop(cc, echan->ch_num);
vchan_cookie_complete(&edesc->vdesc);
echan->edesc = NULL;
} else {
dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
- edma_pause(echan->ch_num);
+ edma_pause(cc, echan->ch_num);
/* Update statistics for tx_status */
edesc->residue -= edesc->sg_len;
@@ -744,7 +746,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
}
break;
case EDMA_DMA_CC_ERROR:
- edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
+ edma_read_slot(cc, echan->slot[0], &p);
/*
* Issue later based on missed flag which will be sure
@@ -767,10 +769,10 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
* missed, so its safe to issue it here.
*/
dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
- edma_clean_channel(echan->ch_num);
- edma_stop(echan->ch_num);
- edma_start(echan->ch_num);
- edma_trigger_channel(echan->ch_num);
+ edma_clean_channel(cc, echan->ch_num);
+ edma_stop(cc, echan->ch_num);
+ edma_start(cc, echan->ch_num);
+ edma_trigger_channel(cc, echan->ch_num);
}
break;
default:
@@ -789,8 +791,8 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
int a_ch_num;
LIST_HEAD(descs);
- a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
- echan, EVENTQ_DEFAULT);
+ a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num,
+ edma_callback, echan, EVENTQ_DEFAULT);
if (a_ch_num < 0) {
ret = -ENODEV;
@@ -814,7 +816,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
return 0;
err_wrong_chan:
- edma_free_channel(a_ch_num);
+ edma_free_channel(echan->ecc->cc, a_ch_num);
err_no_chan:
return ret;
}
@@ -827,21 +829,21 @@ static void edma_free_chan_resources(struct dma_chan *chan)
int i;
/* Terminate transfers */
- edma_stop(echan->ch_num);
+ edma_stop(echan->ecc->cc, echan->ch_num);
vchan_free_chan_resources(&echan->vchan);
/* Free EDMA PaRAM slots */
for (i = 1; i < EDMA_MAX_SLOTS; i++) {
if (echan->slot[i] >= 0) {
- edma_free_slot(echan->slot[i]);
+ edma_free_slot(echan->ecc->cc, echan->slot[i]);
echan->slot[i] = -1;
}
}
/* Free EDMA channel */
if (echan->alloced) {
- edma_free_channel(echan->ch_num);
+ edma_free_channel(echan->ecc->cc, echan->ch_num);
echan->alloced = false;
}
@@ -871,7 +873,8 @@ static u32 edma_residue(struct edma_desc *edesc)
* We always read the dst/src position from the first RamPar
* pset. That's the one which is active now.
*/
- pos = edma_get_position(edesc->echan->slot[0], dst);
+ pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0],
+ dst);
/*
* Cyclic is simple. Just subtract pset[0].addr from pos.
@@ -1008,8 +1011,12 @@ static int edma_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ ecc->cc = edma_get_data(pdev->dev.parent);
+ if (!ecc->cc)
+ return -ENODEV;
+
ecc->ctlr = pdev->id;
- ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
+ ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
return ecc->dummy_slot;
@@ -1042,7 +1049,7 @@ static int edma_probe(struct platform_device *pdev)
return 0;
err_reg1:
- edma_free_slot(ecc->dummy_slot);
+ edma_free_slot(ecc->cc, ecc->dummy_slot);
return ret;
}
@@ -1055,7 +1062,7 @@ static int edma_remove(struct platform_device *pdev)
if (parent_node)
of_dma_controller_free(parent_node);
dma_async_device_unregister(&ecc->dma_slave);
- edma_free_slot(ecc->dummy_slot);
+ edma_free_slot(ecc->cc, ecc->dummy_slot);
return 0;
}
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index c1862423b356..466021c03169 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -92,32 +92,40 @@ enum dma_event_q {
#define EDMA_MAX_CC 2
+struct edma;
+
+struct edma *edma_get_data(struct device *edma_dev);
+
/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
+int edma_alloc_channel(struct edma *cc, int channel,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
+void edma_free_channel(struct edma *cc, unsigned channel);
/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
+int edma_alloc_slot(struct edma *cc, int slot);
+void edma_free_slot(struct edma *cc, unsigned slot);
/* calls that operate on part of a parameter RAM slot */
-dma_addr_t edma_get_position(unsigned slot, bool dst);
-void edma_link(unsigned from, unsigned to);
+dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst);
+void edma_link(struct edma *cc, unsigned from, unsigned to);
/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
+void edma_write_slot(struct edma *cc, unsigned slot,
+ const struct edmacc_param *params);
+void edma_read_slot(struct edma *cc, unsigned slot,
+ struct edmacc_param *params);
/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
+int edma_start(struct edma *cc, unsigned channel);
+void edma_stop(struct edma *cc, unsigned channel);
+void edma_clean_channel(struct edma *cc, unsigned channel);
+void edma_pause(struct edma *cc, unsigned channel);
+void edma_resume(struct edma *cc, unsigned channel);
+int edma_trigger_channel(struct edma *cc, unsigned channel);
-void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no);
+void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
+ enum dma_event_q eventq_no);
struct edma_rsv_info {
@@ -141,6 +149,4 @@ struct edma_soc_info {
const s16 (*xbar_chans)[2];
};
-int edma_trigger_channel(unsigned);
-
#endif
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 08/21] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (6 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 07/21] ARM/dmaengine: edma: Public API to use private struct pointer Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:40 ` Arnd Bergmann
2015-09-10 8:37 ` [PATCH 09/21] ARM: davinci: Add set dma_mask to eDMA devices Peter Ujfalusi
` (13 subsequent siblings)
21 siblings, 1 reply; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
bla-bla and bla
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 22 +++++-----------------
drivers/dma/edma.c | 17 ++++++++---------
2 files changed, 13 insertions(+), 26 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 15b68ce98ec7..0f29997c62df 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1227,24 +1227,7 @@ static int edma_probe(struct platform_device *pdev)
.parent = &pdev->dev,
};
- /* When booting with DT the pdev->id is -1 */
- if (dev_id < 0)
- dev_id = arch_num_cc;
-
- if (dev_id >= EDMA_MAX_CC) {
- dev_err(dev,
- "eDMA3 with device id 0 and 1 is supported (id: %d)\n",
- dev_id);
- return -EINVAL;
- }
-
if (node) {
- /* Check if this is a second instance registered */
- if (arch_num_cc) {
- dev_err(dev, "only one EDMA instance is supported via DT\n");
- return -ENODEV;
- }
-
info = edma_setup_info_from_dt(dev, node);
if (IS_ERR(info)) {
dev_err(dev, "failed to get DT data\n");
@@ -1278,6 +1261,11 @@ static int edma_probe(struct platform_device *pdev)
cc->dev = dev;
cc->id = dev_id;
+ /* When booting with DT the pdev->id is -1 */
+ if (dev_id < 0) {
+ cc->id = 0;
+ dev_id = arch_num_cc;
+ }
dev_set_drvdata(dev, cc);
cc->base = devm_ioremap_resource(dev, mem);
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 53d48b2a700d..fc91ab9dd1bb 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -991,14 +991,12 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
INIT_LIST_HEAD(&dma->channels);
}
-static struct of_dma_filter_info edma_filter_info = {
- .filter_fn = edma_filter_fn,
-};
-
static int edma_probe(struct platform_device *pdev)
{
struct edma_cc *ecc;
struct device_node *parent_node = pdev->dev.parent->of_node;
+ struct platform_device *parent_pdev =
+ to_platform_device(pdev->dev.parent);
int ret;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
@@ -1015,7 +1013,10 @@ static int edma_probe(struct platform_device *pdev)
if (!ecc->cc)
return -ENODEV;
- ecc->ctlr = pdev->id;
+ ecc->ctlr = parent_pdev->id;
+ if (ecc->ctlr < 0)
+ ecc->ctlr = 0;
+
ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
@@ -1038,10 +1039,8 @@ static int edma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ecc);
if (parent_node) {
- dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
- dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
- of_dma_controller_register(parent_node, of_dma_simple_xlate,
- &edma_filter_info);
+ of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id,
+ &ecc->dma_slave);
}
dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 08/21] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers
2015-09-10 8:37 ` [PATCH 08/21] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Peter Ujfalusi
@ 2015-09-10 8:40 ` Arnd Bergmann
2015-09-10 9:09 ` Peter Ujfalusi
0 siblings, 1 reply; 27+ messages in thread
From: Arnd Bergmann @ 2015-09-10 8:40 UTC (permalink / raw)
To: Peter Ujfalusi
Cc: vinod.koul, nsekhar, linux, olof, linux-arm-kernel, linux-kernel,
linux-omap, dmaengine
On Thursday 10 September 2015 11:37:37 Peter Ujfalusi wrote:
> bla-bla and bla
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
You may want to expand on that a bit.
Arnd
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 08/21] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers
2015-09-10 8:40 ` Arnd Bergmann
@ 2015-09-10 9:09 ` Peter Ujfalusi
0 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 9:09 UTC (permalink / raw)
To: Arnd Bergmann
Cc: vinod.koul, nsekhar, linux, olof, linux-arm-kernel, linux-kernel,
linux-omap, dmaengine
On 09/10/2015 11:40 AM, Arnd Bergmann wrote:
> On Thursday 10 September 2015 11:37:37 Peter Ujfalusi wrote:
>> bla-bla and bla
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
>
> You may want to expand on that a bit.
I'm sorry about this.. I believed I did checked all the commit message.
Will be updated in v2.
--
Péter
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 09/21] ARM: davinci: Add set dma_mask to eDMA devices
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (7 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 08/21] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:45 ` Arnd Bergmann
2015-09-10 8:37 ` [PATCH 10/21] ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine Peter Ujfalusi
` (12 subsequent siblings)
21 siblings, 1 reply; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
The upcoming change to merge the arch/arm/common/edma.c into
drivers/dma/edma.c will need this change when booting daVinci devices in
no DT mode.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/mach-davinci/devices-da8xx.c | 8 ++++++++
arch/arm/mach-davinci/dm355.c | 8 +++++++-
arch/arm/mach-davinci/dm644x.c | 8 +++++++-
arch/arm/mach-davinci/dm646x.c | 8 +++++++-
4 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 9ae049ae816a..495e9293ed2a 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -213,21 +213,29 @@ static struct resource da850_edma1_resources[] = {
},
};
+static u64 da8xx_edma0_dmamask = DMA_BIT_MASK(32);
+
static struct platform_device da8xx_edma0_device = {
.name = "edma",
.id = 0,
.dev = {
.platform_data = &da8xx_edma0_pdata,
+ .dma_mask = &da8xx_edma0_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(da8xx_edma0_resources),
.resource = da8xx_edma0_resources,
};
+static u64 da850_edma1_dmamask = DMA_BIT_MASK(32);
+
static struct platform_device da850_edma1_device = {
.name = "edma",
.id = 1,
.dev = {
.platform_data = &da850_edma1_pdata,
+ .dma_mask = &da850_edma1_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(da850_edma1_resources),
.resource = da850_edma1_resources,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a50bb9c66952..0f8c0ab48872 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -613,10 +613,16 @@ static struct resource edma_resources[] = {
/* not using (or muxing) TC*_ERR */
};
+static u64 dm355_edma_dmamask = DMA_BIT_MASK(32);
+
static struct platform_device dm355_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = &dm355_edma_pdata,
+ .dev = {
+ .platform_data = &dm355_edma_pdata,
+ .dma_mask = &dm355_edma_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d759ca8e58e8..fc8950e5a9a0 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -542,10 +542,16 @@ static struct resource edma_resources[] = {
/* not using TC*_ERR */
};
+static u64 dm644x_edma_dmamask = DMA_BIT_MASK(32);
+
static struct platform_device dm644x_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = &dm644x_edma_pdata,
+ .dev = {
+ .platform_data = &dm644x_edma_pdata,
+ .dma_mask = &dm644x_edma_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 219ebc8f674a..77df905949bc 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -589,10 +589,16 @@ static struct resource edma_resources[] = {
/* not using TC*_ERR */
};
+static u64 dm646x_edma_dmamask = DMA_BIT_MASK(32);
+
static struct platform_device dm646x_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = &dm646x_edma_pdata,
+ .dev = {
+ .platform_data = &dm646x_edma_pdata,
+ .dma_mask = &dm646x_edma_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 09/21] ARM: davinci: Add set dma_mask to eDMA devices
2015-09-10 8:37 ` [PATCH 09/21] ARM: davinci: Add set dma_mask to eDMA devices Peter Ujfalusi
@ 2015-09-10 8:45 ` Arnd Bergmann
2015-09-10 9:13 ` Peter Ujfalusi
0 siblings, 1 reply; 27+ messages in thread
From: Arnd Bergmann @ 2015-09-10 8:45 UTC (permalink / raw)
To: Peter Ujfalusi
Cc: vinod.koul, nsekhar, linux, olof, linux-arm-kernel, linux-kernel,
linux-omap, dmaengine
On Thursday 10 September 2015 11:37:38 Peter Ujfalusi wrote:
> +static u64 da8xx_edma0_dmamask = DMA_BIT_MASK(32);
> +
> static struct platform_device da8xx_edma0_device = {
> .name = "edma",
> .id = 0,
> .dev = {
> .platform_data = &da8xx_edma0_pdata,
> + .dma_mask = &da8xx_edma0_dmamask,
> + .coherent_dma_mask = DMA_BIT_MASK(32),
> },
> .num_resources = ARRAY_SIZE(da8xx_edma0_resources),
> .resource = da8xx_edma0_resources,
> };
While this is technically correct for all I can tell, could you
convert it to use __initconst platform_device_info and
platform_device_register_full() instead?
statically declaring platform_devices has been frowned upon for a long
time (even though a lot of arm platforms still do it), and statically
declaring the dma mask seems worse to me (and yes, I realize we also
do that elsewhere).
Arnd
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 09/21] ARM: davinci: Add set dma_mask to eDMA devices
2015-09-10 8:45 ` Arnd Bergmann
@ 2015-09-10 9:13 ` Peter Ujfalusi
0 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 9:13 UTC (permalink / raw)
To: Arnd Bergmann
Cc: vinod.koul, nsekhar, linux, olof, linux-arm-kernel, linux-kernel,
linux-omap, dmaengine
On 09/10/2015 11:45 AM, Arnd Bergmann wrote:
> On Thursday 10 September 2015 11:37:38 Peter Ujfalusi wrote:
>> +static u64 da8xx_edma0_dmamask = DMA_BIT_MASK(32);
>> +
>> static struct platform_device da8xx_edma0_device = {
>> .name = "edma",
>> .id = 0,
>> .dev = {
>> .platform_data = &da8xx_edma0_pdata,
>> + .dma_mask = &da8xx_edma0_dmamask,
>> + .coherent_dma_mask = DMA_BIT_MASK(32),
>> },
>> .num_resources = ARRAY_SIZE(da8xx_edma0_resources),
>> .resource = da8xx_edma0_resources,
>> };
>
> While this is technically correct for all I can tell, could you
> convert it to use __initconst platform_device_info and
> platform_device_register_full() instead?
Yes, I can do that for the eDMAs. I was also thought about this, but looking
around the mach-davinci, I thought to stick with this mode.
> statically declaring platform_devices has been frowned upon for a long
> time (even though a lot of arm platforms still do it), and statically
> declaring the dma mask seems worse to me (and yes, I realize we also
> do that elsewhere).
Will be part of v2.
--
Péter
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 10/21] ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (8 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 09/21] ARM: davinci: Add set dma_mask to eDMA devices Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 11/21] dmaengine: edma: Allocate memory dynamically for bitmaps and structures Peter Ujfalusi
` (11 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Move the code out from arch/arm/common and merge it inside of the dmaengine
driver.
This change is done with as minimal change to the code as possible to avoid
any possibilities to introducing regression.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/Kconfig | 1 -
arch/arm/common/Kconfig | 3 -
arch/arm/common/Makefile | 1 -
arch/arm/common/edma.c | 1432 ------------------------------------
arch/arm/mach-omap2/Kconfig | 1 -
drivers/dma/Kconfig | 1 -
drivers/dma/edma.c | 1409 +++++++++++++++++++++++++++++++++--
include/linux/platform_data/edma.h | 74 --
8 files changed, 1351 insertions(+), 1571 deletions(-)
delete mode 100644 arch/arm/common/edma.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72ad724c67ae..513e38701418 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -736,7 +736,6 @@ config ARCH_DAVINCI
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select HAVE_IDE
- select TI_PRIV_EDMA
select USE_OF
select ZONE_DMA
help
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index c3a4e9ceba34..9353184d730d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -17,6 +17,3 @@ config SHARP_PARAM
config SHARP_SCOOP
bool
-
-config TI_PRIV_EDMA
- bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 6ee5959a813b..27f23b15b1ea 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -15,6 +15,5 @@ obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
CFLAGS_REMOVE_mcpm_entry.o = -pg
AFLAGS_mcpm_head.o := -march=armv7-a
AFLAGS_vlock.o := -march=armv7-a
-obj-$(CONFIG_TI_PRIV_EDMA) += edma.o
obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o
obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
deleted file mode 100644
index 0f29997c62df..000000000000
--- a/arch/arm/common/edma.c
+++ /dev/null
@@ -1,1432 +0,0 @@
-/*
- * EDMA3 support for DaVinci
- *
- * Copyright (C) 2006-2009 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/edma.h>
-#include <linux/dma-mapping.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
-#include <linux/pm_runtime.h>
-
-#include <linux/platform_data/edma.h>
-
-/* Offsets matching "struct edmacc_param" */
-#define PARM_OPT 0x00
-#define PARM_SRC 0x04
-#define PARM_A_B_CNT 0x08
-#define PARM_DST 0x0c
-#define PARM_SRC_DST_BIDX 0x10
-#define PARM_LINK_BCNTRLD 0x14
-#define PARM_SRC_DST_CIDX 0x18
-#define PARM_CCNT 0x1c
-
-#define PARM_SIZE 0x20
-
-/* Offsets for EDMA CC global channel registers and their shadows */
-#define SH_ER 0x00 /* 64 bits */
-#define SH_ECR 0x08 /* 64 bits */
-#define SH_ESR 0x10 /* 64 bits */
-#define SH_CER 0x18 /* 64 bits */
-#define SH_EER 0x20 /* 64 bits */
-#define SH_EECR 0x28 /* 64 bits */
-#define SH_EESR 0x30 /* 64 bits */
-#define SH_SER 0x38 /* 64 bits */
-#define SH_SECR 0x40 /* 64 bits */
-#define SH_IER 0x50 /* 64 bits */
-#define SH_IECR 0x58 /* 64 bits */
-#define SH_IESR 0x60 /* 64 bits */
-#define SH_IPR 0x68 /* 64 bits */
-#define SH_ICR 0x70 /* 64 bits */
-#define SH_IEVAL 0x78
-#define SH_QER 0x80
-#define SH_QEER 0x84
-#define SH_QEECR 0x88
-#define SH_QEESR 0x8c
-#define SH_QSER 0x90
-#define SH_QSECR 0x94
-#define SH_SIZE 0x200
-
-/* Offsets for EDMA CC global registers */
-#define EDMA_REV 0x0000
-#define EDMA_CCCFG 0x0004
-#define EDMA_QCHMAP 0x0200 /* 8 registers */
-#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
-#define EDMA_QDMAQNUM 0x0260
-#define EDMA_QUETCMAP 0x0280
-#define EDMA_QUEPRI 0x0284
-#define EDMA_EMR 0x0300 /* 64 bits */
-#define EDMA_EMCR 0x0308 /* 64 bits */
-#define EDMA_QEMR 0x0310
-#define EDMA_QEMCR 0x0314
-#define EDMA_CCERR 0x0318
-#define EDMA_CCERRCLR 0x031c
-#define EDMA_EEVAL 0x0320
-#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
-#define EDMA_QRAE 0x0380 /* 4 registers */
-#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
-#define EDMA_QSTAT 0x0600 /* 2 registers */
-#define EDMA_QWMTHRA 0x0620
-#define EDMA_QWMTHRB 0x0624
-#define EDMA_CCSTAT 0x0640
-
-#define EDMA_M 0x1000 /* global channel registers */
-#define EDMA_ECR 0x1008
-#define EDMA_ECRH 0x100C
-#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
-#define EDMA_PARM 0x4000 /* 128 param entries */
-
-#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
-
-#define EDMA_DCHMAP 0x0100 /* 64 registers */
-
-/* CCCFG register */
-#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
-#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
-#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
-#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
-#define CHMAP_EXIST BIT(24)
-
-#define EDMA_MAX_DMACH 64
-#define EDMA_MAX_PARAMENTRY 512
-
-/*****************************************************************************/
-struct edma {
- struct device *dev;
- void __iomem *base;
-
- /* how many dma resources of each type */
- unsigned num_channels;
- unsigned num_region;
- unsigned num_slots;
- unsigned num_tc;
- enum dma_event_q default_queue;
-
- /* list of channels with no even trigger; terminated by "-1" */
- const s8 *noevent;
-
- struct edma_soc_info *info;
- int id;
- bool unused_chan_list_done;
- /* The edma_inuse bit for each PaRAM slot is clear unless the
- * channel is in use ... by ARM or DSP, for QDMA, or whatever.
- */
- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-
- /* The edma_unused bit for each channel is clear unless
- * it is not being used on this platform. It uses a bit
- * of SOC-specific initialization code.
- */
- DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
-
- struct dma_interrupt_data {
- void (*callback)(unsigned channel, unsigned short ch_status,
- void *data);
- void *data;
- } intr_data[EDMA_MAX_DMACH];
-};
-/*****************************************************************************/
-
-static inline unsigned int edma_read(struct edma *cc, int offset)
-{
- return (unsigned int)__raw_readl(cc->base + offset);
-}
-
-static inline void edma_write(struct edma *cc, int offset, int val)
-{
- __raw_writel(val, cc->base + offset);
-}
-static inline void edma_modify(struct edma *cc, int offset, unsigned and,
- unsigned or)
-{
- unsigned val = edma_read(cc, offset);
- val &= and;
- val |= or;
- edma_write(cc, offset, val);
-}
-static inline void edma_and(struct edma *cc, int offset, unsigned and)
-{
- unsigned val = edma_read(cc, offset);
- val &= and;
- edma_write(cc, offset, val);
-}
-static inline void edma_or(struct edma *cc, int offset, unsigned or)
-{
- unsigned val = edma_read(cc, offset);
- val |= or;
- edma_write(cc, offset, val);
-}
-static inline unsigned int edma_read_array(struct edma *cc, int offset, int i)
-{
- return edma_read(cc, offset + (i << 2));
-}
-static inline void edma_write_array(struct edma *cc, int offset, int i,
- unsigned val)
-{
- edma_write(cc, offset + (i << 2), val);
-}
-static inline void edma_modify_array(struct edma *cc, int offset, int i,
- unsigned and, unsigned or)
-{
- edma_modify(cc, offset + (i << 2), and, or);
-}
-static inline void edma_or_array(struct edma *cc, int offset, int i, unsigned or)
-{
- edma_or(cc, offset + (i << 2), or);
-}
-static inline void edma_or_array2(struct edma *cc, int offset, int i, int j,
- unsigned or)
-{
- edma_or(cc, offset + ((i*2 + j) << 2), or);
-}
-static inline void edma_write_array2(struct edma *cc, int offset, int i, int j,
- unsigned val)
-{
- edma_write(cc, offset + ((i*2 + j) << 2), val);
-}
-static inline unsigned int edma_shadow0_read(struct edma *cc, int offset)
-{
- return edma_read(cc, EDMA_SHADOW0 + offset);
-}
-static inline unsigned int edma_shadow0_read_array(struct edma *cc, int offset,
- int i)
-{
- return edma_read(cc, EDMA_SHADOW0 + offset + (i << 2));
-}
-static inline void edma_shadow0_write(struct edma *cc, int offset, unsigned val)
-{
- edma_write(cc, EDMA_SHADOW0 + offset, val);
-}
-static inline void edma_shadow0_write_array(struct edma *cc, int offset, int i,
- unsigned val)
-{
- edma_write(cc, EDMA_SHADOW0 + offset + (i << 2), val);
-}
-static inline unsigned int edma_parm_read(struct edma *cc, int offset,
- int param_no)
-{
- return edma_read(cc, EDMA_PARM + offset + (param_no << 5));
-}
-static inline void edma_parm_write(struct edma *cc, int offset, int param_no,
- unsigned val)
-{
- edma_write(cc, EDMA_PARM + offset + (param_no << 5), val);
-}
-static inline void edma_parm_modify(struct edma *cc, int offset, int param_no,
- unsigned and, unsigned or)
-{
- edma_modify(cc, EDMA_PARM + offset + (param_no << 5), and, or);
-}
-static inline void edma_parm_and(struct edma *cc, int offset, int param_no,
- unsigned and)
-{
- edma_and(cc, EDMA_PARM + offset + (param_no << 5), and);
-}
-static inline void edma_parm_or(struct edma *cc, int offset, int param_no,
- unsigned or)
-{
- edma_or(cc, EDMA_PARM + offset + (param_no << 5), or);
-}
-
-static inline void set_bits(int offset, int len, unsigned long *p)
-{
- for (; len > 0; len--)
- set_bit(offset + (len - 1), p);
-}
-
-static inline void clear_bits(int offset, int len, unsigned long *p)
-{
- for (; len > 0; len--)
- clear_bit(offset + (len - 1), p);
-}
-
-/*****************************************************************************/
-static int arch_num_cc;
-
-/* dummy param set used to (re)initialize parameter RAM slots */
-static const struct edmacc_param dummy_paramset = {
- .link_bcntrld = 0xffff,
- .ccnt = 1,
-};
-
-static const struct of_device_id edma_of_ids[] = {
- { .compatible = "ti,edma3", },
- {}
-};
-
-/*****************************************************************************/
-
-static void map_dmach_queue(struct edma *cc, unsigned ch_no,
- enum dma_event_q queue_no)
-{
- int bit = (ch_no & 0x7) * 4;
-
- /* default to low priority queue */
- if (queue_no == EVENTQ_DEFAULT)
- queue_no = cc->default_queue;
-
- queue_no &= 7;
- edma_modify_array(cc, EDMA_DMAQNUM, (ch_no >> 3),
- ~(0x7 << bit), queue_no << bit);
-}
-
-static void assign_priority_to_queue(struct edma *cc, int queue_no,
- int priority)
-{
- int bit = queue_no * 4;
- edma_modify(cc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
-}
-
-/**
- * map_dmach_param - Maps channel number to param entry number
- *
- * This maps the dma channel number to param entry numberter. In
- * other words using the DMA channel mapping registers a param entry
- * can be mapped to any channel
- *
- * Callers are responsible for ensuring the channel mapping logic is
- * included in that particular EDMA variant (Eg : dm646x)
- *
- */
-static void map_dmach_param(struct edma *cc)
-{
- int i;
- for (i = 0; i < EDMA_MAX_DMACH; i++)
- edma_write_array(cc, EDMA_DCHMAP , i , (i << 5));
-}
-
-static inline void setup_dma_interrupt(struct edma *cc, unsigned lch,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data)
-{
- lch = EDMA_CHAN_SLOT(lch);
-
- if (!callback)
- edma_shadow0_write_array(cc, SH_IECR, lch >> 5,
- BIT(lch & 0x1f));
-
- cc->intr_data[lch].callback = callback;
- cc->intr_data[lch].data = data;
-
- if (callback) {
- edma_shadow0_write_array(cc, SH_ICR, lch >> 5, BIT(lch & 0x1f));
- edma_shadow0_write_array(cc, SH_IESR, lch >> 5,
- BIT(lch & 0x1f));
- }
-}
-
-/******************************************************************************
- *
- * DMA interrupt handler
- *
- *****************************************************************************/
-static irqreturn_t dma_irq_handler(int irq, void *data)
-{
- struct edma *cc = data;
- int ctlr;
- u32 sh_ier;
- u32 sh_ipr;
- u32 bank;
-
- ctlr = cc->id;
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(cc->dev, "dma_irq_handler\n");
-
- sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 0);
- if (!sh_ipr) {
- sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 1);
- if (!sh_ipr)
- return IRQ_NONE;
- sh_ier = edma_shadow0_read_array(cc, SH_IER, 1);
- bank = 1;
- } else {
- sh_ier = edma_shadow0_read_array(cc, SH_IER, 0);
- bank = 0;
- }
-
- do {
- u32 slot;
- u32 channel;
-
- dev_dbg(cc->dev, "IPR%d %08x\n", bank, sh_ipr);
-
- slot = __ffs(sh_ipr);
- sh_ipr &= ~(BIT(slot));
-
- if (sh_ier & BIT(slot)) {
- channel = (bank << 5) | slot;
- /* Clear the corresponding IPR bits */
- edma_shadow0_write_array(cc, SH_ICR, bank, BIT(slot));
- if (cc->intr_data[channel].callback)
- cc->intr_data[channel].callback(
- EDMA_CTLR_CHAN(ctlr, channel),
- EDMA_DMA_COMPLETE,
- cc->intr_data[channel].data);
- }
- } while (sh_ipr);
-
- edma_shadow0_write(cc, SH_IEVAL, 1);
- return IRQ_HANDLED;
-}
-
-/******************************************************************************
- *
- * DMA error interrupt handler
- *
- *****************************************************************************/
-static irqreturn_t dma_ccerr_handler(int irq, void *data)
-{
- struct edma *cc = data;
- int i;
- int ctlr;
- unsigned int cnt = 0;
-
- ctlr = cc->id;
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(cc->dev, "dma_ccerr_handler\n");
-
- if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(cc, EDMA_EMR, 1) == 0) &&
- (edma_read(cc, EDMA_QEMR) == 0) &&
- (edma_read(cc, EDMA_CCERR) == 0))
- return IRQ_NONE;
-
- while (1) {
- int j = -1;
- if (edma_read_array(cc, EDMA_EMR, 0))
- j = 0;
- else if (edma_read_array(cc, EDMA_EMR, 1))
- j = 1;
- if (j >= 0) {
- dev_dbg(cc->dev, "EMR%d %08x\n", j,
- edma_read_array(cc, EDMA_EMR, j));
- for (i = 0; i < 32; i++) {
- int k = (j << 5) + i;
- if (edma_read_array(cc, EDMA_EMR, j) &
- BIT(i)) {
- /* Clear the corresponding EMR bits */
- edma_write_array(cc, EDMA_EMCR, j,
- BIT(i));
- /* Clear any SER */
- edma_shadow0_write_array(cc, SH_SECR,
- j, BIT(i));
- if (cc->intr_data[k].callback) {
- cc->intr_data[k].callback(
- EDMA_CTLR_CHAN(ctlr, k),
- EDMA_DMA_CC_ERROR,
- cc->intr_data[k].data);
- }
- }
- }
- } else if (edma_read(cc, EDMA_QEMR)) {
- dev_dbg(cc->dev, "QEMR %02x\n",
- edma_read(cc, EDMA_QEMR));
- for (i = 0; i < 8; i++) {
- if (edma_read(cc, EDMA_QEMR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(cc, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(cc, SH_QSECR,
- BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- } else if (edma_read(cc, EDMA_CCERR)) {
- dev_dbg(cc->dev, "CCERR %08x\n",
- edma_read(cc, EDMA_CCERR));
- /* FIXME: CCERR.BIT(16) ignored! much better
- * to just write CCERRCLR with CCERR value...
- */
- for (i = 0; i < 8; i++) {
- if (edma_read(cc, EDMA_CCERR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(cc, EDMA_CCERRCLR, BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- }
- if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(cc, EDMA_EMR, 1) == 0) &&
- (edma_read(cc, EDMA_QEMR) == 0) &&
- (edma_read(cc, EDMA_CCERR) == 0))
- break;
- cnt++;
- if (cnt > 10)
- break;
- }
- edma_write(cc, EDMA_EEVAL, 1);
- return IRQ_HANDLED;
-}
-
-static int prepare_unused_channel_list(struct device *dev, void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct edma *cc = data;
- int i, count;
- struct of_phandle_args dma_spec;
-
- if (dev->of_node) {
- struct platform_device *dma_pdev;
-
- count = of_property_count_strings(dev->of_node, "dma-names");
- if (count < 0)
- return 0;
- for (i = 0; i < count; i++) {
-
- if (of_parse_phandle_with_args(dev->of_node, "dmas",
- "#dma-cells", i,
- &dma_spec))
- continue;
-
- if (!of_match_node(edma_of_ids, dma_spec.np)) {
- of_node_put(dma_spec.np);
- continue;
- }
-
- dma_pdev = of_find_device_by_node(dma_spec.np);
- if (&dma_pdev->dev != cc->dev)
- continue;
-
- clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
- cc->edma_unused);
- of_node_put(dma_spec.np);
- }
- return 0;
- }
-
- /* For non-OF case */
- for (i = 0; i < pdev->num_resources; i++) {
- struct resource *res = &pdev->resource[i];
-
- if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
- clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
- cc->edma_unused);
- }
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------*/
-
-/* Resource alloc/free: dma channels, parameter RAM slots */
-
-/**
- * edma_alloc_channel - allocate DMA channel and paired parameter RAM
- * @channel: specific channel to allocate; negative for "any unmapped channel"
- * @callback: optional; to be issued on DMA completion or errors
- * @data: passed to callback
- * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
- * Controller (TC) executes requests using this channel. Use
- * EVENTQ_DEFAULT unless you really need a high priority queue.
- *
- * This allocates a DMA channel and its associated parameter RAM slot.
- * The parameter RAM is initialized to hold a dummy transfer.
- *
- * Normal use is to pass a specific channel number as @channel, to make
- * use of hardware events mapped to that channel. When the channel will
- * be used only for software triggering or event chaining, channels not
- * mapped to hardware events (or mapped to unused events) are preferable.
- *
- * DMA transfers start from a channel using edma_start(), or by
- * chaining. When the transfer described in that channel's parameter RAM
- * slot completes, that slot's data may be reloaded through a link.
- *
- * DMA errors are only reported to the @callback associated with the
- * channel driving that transfer, but transfer completion callbacks can
- * be sent to another channel under control of the TCC field in
- * the option word of the transfer's parameter RAM set. Drivers must not
- * use DMA transfer completion callbacks for channels they did not allocate.
- * (The same applies to TCC codes used in transfer chaining.)
- *
- * Returns the number of the channel, else negative errno.
- */
-int edma_alloc_channel(struct edma *cc, int channel,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data,
- enum dma_event_q eventq_no)
-{
- unsigned done = 0;
- int ret = 0;
-
- if (!cc->unused_chan_list_done) {
- /*
- * Scan all the platform devices to find out the EDMA channels
- * used and clear them in the unused list, making the rest
- * available for ARM usage.
- */
- ret = bus_for_each_dev(&platform_bus_type, NULL, cc,
- prepare_unused_channel_list);
- if (ret < 0)
- return ret;
-
- cc->unused_chan_list_done = true;
- }
-
- if (channel >= 0) {
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n",
- __func__, cc->id, EDMA_CTLR(channel));
- return -EINVAL;
- }
- channel = EDMA_CHAN_SLOT(channel);
- }
-
- if (channel < 0) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(cc->edma_unused,
- cc->num_channels, channel);
- if (channel == cc->num_channels)
- break;
- if (!test_and_set_bit(channel, cc->edma_inuse)) {
- done = 1;
- break;
- }
- channel++;
- }
- if (!done)
- return -ENOMEM;
- } else if (channel >= cc->num_channels) {
- return -EINVAL;
- } else if (test_and_set_bit(channel, cc->edma_inuse)) {
- return -EBUSY;
- }
-
- /* ensure access through shadow region 0 */
- edma_or_array2(cc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
-
- /* ensure no events are pending */
- edma_stop(cc, EDMA_CTLR_CHAN(cc->id, channel));
- memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
- PARM_SIZE);
-
- if (callback)
- setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, channel),
- callback, data);
-
- map_dmach_queue(cc, channel, eventq_no);
-
- return EDMA_CTLR_CHAN(cc->id, channel);
-}
-EXPORT_SYMBOL(edma_alloc_channel);
-
-
-/**
- * edma_free_channel - deallocate DMA channel
- * @channel: dma channel returned from edma_alloc_channel()
- *
- * This deallocates the DMA channel and associated parameter RAM slot
- * allocated by edma_alloc_channel().
- *
- * Callers are responsible for ensuring the channel is inactive, and
- * will not be reactivated by linking, chaining, or software calls to
- * edma_start().
- */
-void edma_free_channel(struct edma *cc, unsigned channel)
-{
-
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return;
- }
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel >= cc->num_channels)
- return;
-
- setup_dma_interrupt(cc, channel, NULL, NULL);
- /* REVISIT should probably take out of shadow region 0 */
-
- memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
- PARM_SIZE);
- clear_bit(channel, cc->edma_inuse);
-}
-EXPORT_SYMBOL(edma_free_channel);
-
-/**
- * edma_alloc_slot - allocate DMA parameter RAM
- * @slot: specific slot to allocate; negative for "any unused slot"
- *
- * This allocates a parameter RAM slot, initializing it to hold a
- * dummy transfer. Slots allocated using this routine have not been
- * mapped to a hardware DMA channel, and will normally be used by
- * linking to them from a slot associated with a DMA channel.
- *
- * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
- * slots may be allocated on behalf of DSP firmware.
- *
- * Returns the number of the slot, else negative errno.
- */
-int edma_alloc_slot(struct edma *cc, int slot)
-{
- if (slot > 0)
- slot = EDMA_CHAN_SLOT(slot);
- if (slot < 0) {
- slot = cc->num_channels;
- for (;;) {
- slot = find_next_zero_bit(cc->edma_inuse, cc->num_slots,
- slot);
- if (slot == cc->num_slots)
- return -ENOMEM;
- if (!test_and_set_bit(slot, cc->edma_inuse))
- break;
- }
- } else if (slot < cc->num_channels || slot >= cc->num_slots) {
- return -EINVAL;
- } else if (test_and_set_bit(slot, cc->edma_inuse)) {
- return -EBUSY;
- }
-
- memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
-
- return slot;
-}
-EXPORT_SYMBOL(edma_alloc_slot);
-
-/**
- * edma_free_slot - deallocate DMA parameter RAM
- * @slot: parameter RAM slot returned from edma_alloc_slot()
- *
- * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
- * Callers are responsible for ensuring the slot is inactive, and will
- * not be activated.
- */
-void edma_free_slot(struct edma *cc, unsigned slot)
-{
-
- slot = EDMA_CHAN_SLOT(slot);
- if (slot < cc->num_channels || slot >= cc->num_slots)
- return;
-
- memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
- clear_bit(slot, cc->edma_inuse);
-}
-EXPORT_SYMBOL(edma_free_slot);
-
-/*-----------------------------------------------------------------------*/
-
-/* Parameter RAM operations (i) -- read/write partial slots */
-
-/**
- * edma_get_position - returns the current transfer point
- * @slot: parameter RAM slot being examined
- * @dst: true selects the dest position, false the source
- *
- * Returns the position of the current active slot
- */
-dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst)
-{
- u32 offs;
-
- slot = EDMA_CHAN_SLOT(slot);
- offs = PARM_OFFSET(slot);
- offs += dst ? PARM_DST : PARM_SRC;
-
- return edma_read(cc, offs);
-}
-
-/**
- * edma_link - link one parameter RAM slot to another
- * @from: parameter RAM slot originating the link
- * @to: parameter RAM slot which is the link target
- *
- * The originating slot should not be part of any active DMA transfer.
- */
-void edma_link(struct edma *cc, unsigned from, unsigned to)
-{
- from = EDMA_CHAN_SLOT(from);
- to = EDMA_CHAN_SLOT(to);
- if (from >= cc->num_slots || to >= cc->num_slots)
- return;
-
- edma_parm_modify(cc, PARM_LINK_BCNTRLD, from, 0xffff0000,
- PARM_OFFSET(to));
-}
-EXPORT_SYMBOL(edma_link);
-
-/*-----------------------------------------------------------------------*/
-
-/* Parameter RAM operations (ii) -- read/write whole parameter sets */
-
-/**
- * edma_write_slot - write parameter RAM data for slot
- * @slot: number of parameter RAM slot being modified
- * @param: data to be written into parameter RAM slot
- *
- * Use this to assign all parameters of a transfer at once. This
- * allows more efficient setup of transfers than issuing multiple
- * calls to set up those parameters in small pieces, and provides
- * complete control over all transfer options.
- */
-void edma_write_slot(struct edma *cc, unsigned slot,
- const struct edmacc_param *param)
-{
- slot = EDMA_CHAN_SLOT(slot);
- if (slot >= cc->num_slots)
- return;
- memcpy_toio(cc->base + PARM_OFFSET(slot), param, PARM_SIZE);
-}
-EXPORT_SYMBOL(edma_write_slot);
-
-/**
- * edma_read_slot - read parameter RAM data from slot
- * @slot: number of parameter RAM slot being copied
- * @param: where to store copy of parameter RAM data
- *
- * Use this to read data from a parameter RAM slot, perhaps to
- * save them as a template for later reuse.
- */
-void edma_read_slot(struct edma *cc, unsigned slot, struct edmacc_param *param)
-{
- slot = EDMA_CHAN_SLOT(slot);
- if (slot >= cc->num_slots)
- return;
- memcpy_fromio(param, cc->base + PARM_OFFSET(slot), PARM_SIZE);
-}
-EXPORT_SYMBOL(edma_read_slot);
-
-/*-----------------------------------------------------------------------*/
-
-/* Various EDMA channel control operations */
-
-/**
- * edma_pause - pause dma on a channel
- * @channel: on which edma_start() has been called
- *
- * This temporarily disables EDMA hardware events on the specified channel,
- * preventing them from triggering new transfers on its behalf
- */
-void edma_pause(struct edma *cc, unsigned channel)
-{
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return;
- }
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < cc->num_channels) {
- unsigned int mask = BIT(channel & 0x1f);
-
- edma_shadow0_write_array(cc, SH_EECR, channel >> 5, mask);
- }
-}
-EXPORT_SYMBOL(edma_pause);
-
-/**
- * edma_resume - resumes dma on a paused channel
- * @channel: on which edma_pause() has been called
- *
- * This re-enables EDMA hardware events on the specified channel.
- */
-void edma_resume(struct edma *cc, unsigned channel)
-{
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return;
- }
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < cc->num_channels) {
- unsigned int mask = BIT(channel & 0x1f);
-
- edma_shadow0_write_array(cc, SH_EESR, channel >> 5, mask);
- }
-}
-EXPORT_SYMBOL(edma_resume);
-
-int edma_trigger_channel(struct edma *cc, unsigned channel)
-{
- unsigned int mask;
-
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return -EINVAL;
- }
- channel = EDMA_CHAN_SLOT(channel);
- mask = BIT(channel & 0x1f);
-
- edma_shadow0_write_array(cc, SH_ESR, (channel >> 5), mask);
-
- pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(cc, SH_ESR, (channel >> 5)));
- return 0;
-}
-EXPORT_SYMBOL(edma_trigger_channel);
-
-/**
- * edma_start - start dma on a channel
- * @channel: channel being activated
- *
- * Channels with event associations will be triggered by their hardware
- * events, and channels without such associations will be triggered by
- * software. (At this writing there is no interface for using software
- * triggers except with channels that don't support hardware triggers.)
- *
- * Returns zero on success, else negative errno.
- */
-int edma_start(struct edma *cc, unsigned channel)
-{
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return -EINVAL;
- }
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < cc->num_channels) {
- int j = channel >> 5;
- unsigned int mask = BIT(channel & 0x1f);
-
- /* EDMA channels without event association */
- if (test_bit(channel, cc->edma_unused)) {
- pr_debug("EDMA: ESR%d %08x\n", j,
- edma_shadow0_read_array(cc, SH_ESR, j));
- edma_shadow0_write_array(cc, SH_ESR, j, mask);
- return 0;
- }
-
- /* EDMA channel with event association */
- pr_debug("EDMA: ER%d %08x\n", j,
- edma_shadow0_read_array(cc, SH_ER, j));
- /* Clear any pending event or error */
- edma_write_array(cc, EDMA_ECR, j, mask);
- edma_write_array(cc, EDMA_EMCR, j, mask);
- /* Clear any SER */
- edma_shadow0_write_array(cc, SH_SECR, j, mask);
- edma_shadow0_write_array(cc, SH_EESR, j, mask);
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(cc, SH_EER, j));
- return 0;
- }
-
- return -EINVAL;
-}
-EXPORT_SYMBOL(edma_start);
-
-/**
- * edma_stop - stops dma on the channel passed
- * @channel: channel being deactivated
- *
- * When @lch is a channel, any active transfer is paused and
- * all pending hardware events are cleared. The current transfer
- * may not be resumed, and the channel's Parameter RAM should be
- * reinitialized before being reused.
- */
-void edma_stop(struct edma *cc, unsigned channel)
-{
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return;
- }
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < cc->num_channels) {
- int j = channel >> 5;
- unsigned int mask = BIT(channel & 0x1f);
-
- edma_shadow0_write_array(cc, SH_EECR, j, mask);
- edma_shadow0_write_array(cc, SH_ECR, j, mask);
- edma_shadow0_write_array(cc, SH_SECR, j, mask);
- edma_write_array(cc, EDMA_EMCR, j, mask);
-
- /* clear possibly pending completion interrupt */
- edma_shadow0_write_array(cc, SH_ICR, j, mask);
-
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(cc, SH_EER, j));
-
- /* REVISIT: consider guarding against inappropriate event
- * chaining by overwriting with dummy_paramset.
- */
- }
-}
-EXPORT_SYMBOL(edma_stop);
-
-/******************************************************************************
- *
- * It cleans ParamEntry qand bring back EDMA to initial state if media has
- * been removed before EDMA has finished.It is usedful for removable media.
- * Arguments:
- * ch_no - channel no
- *
- * Return: zero on success, or corresponding error no on failure
- *
- * FIXME this should not be needed ... edma_stop() should suffice.
- *
- *****************************************************************************/
-
-void edma_clean_channel(struct edma *cc, unsigned channel)
-{
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return;
- }
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < cc->num_channels) {
- int j = (channel >> 5);
- unsigned int mask = BIT(channel & 0x1f);
-
- pr_debug("EDMA: EMR%d %08x\n", j,
- edma_read_array(cc, EDMA_EMR, j));
- edma_shadow0_write_array(cc, SH_ECR, j, mask);
- /* Clear the corresponding EMR bits */
- edma_write_array(cc, EDMA_EMCR, j, mask);
- /* Clear any SER */
- edma_shadow0_write_array(cc, SH_SECR, j, mask);
- edma_write(cc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
- }
-}
-EXPORT_SYMBOL(edma_clean_channel);
-
-/*
- * edma_assign_channel_eventq - move given channel to desired eventq
- * Arguments:
- * channel - channel number
- * eventq_no - queue to move the channel
- *
- * Can be used to move a channel to a selected event queue.
- */
-void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
- enum dma_event_q eventq_no)
-{
- if (cc->id != EDMA_CTLR(channel)) {
- dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
- cc->id, EDMA_CTLR(channel));
- return;
- }
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel >= cc->num_channels)
- return;
-
- /* default to low priority queue */
- if (eventq_no == EVENTQ_DEFAULT)
- eventq_no = cc->default_queue;
- if (eventq_no >= cc->num_tc)
- return;
-
- map_dmach_queue(cc, channel, eventq_no);
-}
-EXPORT_SYMBOL(edma_assign_channel_eventq);
-
-struct edma *edma_get_data(struct device *edma_dev)
-{
- return dev_get_drvdata(edma_dev);
-}
-
-
-static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
- struct edma *edma_cc, int cc_id)
-{
- int i;
- u32 value, cccfg;
- s8 (*queue_priority_map)[2];
-
- /* Decode the eDMA3 configuration from CCCFG register */
- cccfg = edma_read(edma_cc, EDMA_CCCFG);
-
- value = GET_NUM_REGN(cccfg);
- edma_cc->num_region = BIT(value);
-
- value = GET_NUM_DMACH(cccfg);
- edma_cc->num_channels = BIT(value + 1);
-
- value = GET_NUM_PAENTRY(cccfg);
- edma_cc->num_slots = BIT(value + 4);
-
- value = GET_NUM_EVQUE(cccfg);
- edma_cc->num_tc = value + 1;
-
- dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
- cccfg);
- dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
- dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
- dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
- dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
-
- /* Nothing need to be done if queue priority is provided */
- if (pdata->queue_priority_mapping)
- return 0;
-
- /*
- * Configure TC/queue priority as follows:
- * Q0 - priority 0
- * Q1 - priority 1
- * Q2 - priority 2
- * ...
- * The meaning of priority numbers: 0 highest priority, 7 lowest
- * priority. So Q0 is the highest priority queue and the last queue has
- * the lowest priority.
- */
- queue_priority_map = devm_kzalloc(dev,
- (edma_cc->num_tc + 1) * sizeof(s8),
- GFP_KERNEL);
- if (!queue_priority_map)
- return -ENOMEM;
-
- for (i = 0; i < edma_cc->num_tc; i++) {
- queue_priority_map[i][0] = i;
- queue_priority_map[i][1] = i;
- }
- queue_priority_map[i][0] = -1;
- queue_priority_map[i][1] = -1;
-
- pdata->queue_priority_mapping = queue_priority_map;
- /* Default queue has the lowest priority */
- pdata->default_queue = i - 1;
-
- return 0;
-}
-
-#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
-
-static int edma_xbar_event_map(struct device *dev, struct device_node *node,
- struct edma_soc_info *pdata, size_t sz)
-{
- const char pname[] = "ti,edma-xbar-event-map";
- struct resource res;
- void __iomem *xbar;
- s16 (*xbar_chans)[2];
- size_t nelm = sz / sizeof(s16);
- u32 shift, offset, mux;
- int ret, i;
-
- xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
- if (!xbar_chans)
- return -ENOMEM;
-
- ret = of_address_to_resource(node, 1, &res);
- if (ret)
- return -ENOMEM;
-
- xbar = devm_ioremap(dev, res.start, resource_size(&res));
- if (!xbar)
- return -ENOMEM;
-
- ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
- if (ret)
- return -EIO;
-
- /* Invalidate last entry for the other user of this mess */
- nelm >>= 1;
- xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
-
- for (i = 0; i < nelm; i++) {
- shift = (xbar_chans[i][1] & 0x03) << 3;
- offset = xbar_chans[i][1] & 0xfffffffc;
- mux = readl(xbar + offset);
- mux &= ~(0xff << shift);
- mux |= xbar_chans[i][0] << shift;
- writel(mux, (xbar + offset));
- }
-
- pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
- return 0;
-}
-
-static int edma_of_parse_dt(struct device *dev,
- struct device_node *node,
- struct edma_soc_info *pdata)
-{
- int ret = 0;
- struct property *prop;
- size_t sz;
- struct edma_rsv_info *rsv_info;
-
- rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
- if (!rsv_info)
- return -ENOMEM;
- pdata->rsv = rsv_info;
-
- prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
- if (prop)
- ret = edma_xbar_event_map(dev, node, pdata, sz);
-
- return ret;
-}
-
-static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
- struct device_node *node)
-{
- struct edma_soc_info *info;
- int ret;
-
- info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
- if (!info)
- return ERR_PTR(-ENOMEM);
-
- ret = edma_of_parse_dt(dev, node, info);
- if (ret)
- return ERR_PTR(ret);
-
- return info;
-}
-#else
-static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
- struct device_node *node)
-{
- return ERR_PTR(-ENOSYS);
-}
-#endif
-
-static int edma_probe(struct platform_device *pdev)
-{
- struct edma_soc_info *info = pdev->dev.platform_data;
- s8 (*queue_priority_mapping)[2];
- int i, off, ln;
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
- const s16 (*xbar_chans)[2];
- int irq;
- char *irq_name;
- struct resource *mem;
- struct device_node *node = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- int dev_id = pdev->id;
- struct edma *cc;
- int ret;
- struct platform_device_info edma_dev_info = {
- .name = "edma-dma-engine",
- .dma_mask = DMA_BIT_MASK(32),
- .parent = &pdev->dev,
- };
-
- if (node) {
- info = edma_setup_info_from_dt(dev, node);
- if (IS_ERR(info)) {
- dev_err(dev, "failed to get DT data\n");
- return PTR_ERR(info);
- }
- }
-
- if (!info)
- return -ENODEV;
-
- pm_runtime_enable(dev);
- ret = pm_runtime_get_sync(dev);
- if (ret < 0) {
- dev_err(dev, "pm_runtime_get_sync() failed\n");
- return ret;
- }
-
- mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
- if (!mem) {
- dev_dbg(dev, "mem resource not found, using index 0\n");
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!mem) {
- dev_err(dev, "no mem resource?\n");
- return -ENODEV;
- }
- }
-
- cc = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
- if (!cc)
- return -ENOMEM;
-
- cc->dev = dev;
- cc->id = dev_id;
- /* When booting with DT the pdev->id is -1 */
- if (dev_id < 0) {
- cc->id = 0;
- dev_id = arch_num_cc;
- }
- dev_set_drvdata(dev, cc);
-
- cc->base = devm_ioremap_resource(dev, mem);
- if (IS_ERR(cc->base))
- return PTR_ERR(cc->base);
-
- /* Get eDMA3 configuration from IP */
- ret = edma_setup_from_hw(dev, info, cc, dev_id);
- if (ret)
- return ret;
-
- cc->default_queue = info->default_queue;
-
- for (i = 0; i < cc->num_slots; i++)
- memcpy_toio(cc->base + PARM_OFFSET(i), &dummy_paramset,
- PARM_SIZE);
-
- /* Mark all channels as unused */
- memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused));
-
- if (info->rsv) {
-
- /* Clear the reserved channels in unused list */
- rsv_chans = info->rsv->rsv_chans;
- if (rsv_chans) {
- for (i = 0; rsv_chans[i][0] != -1; i++) {
- off = rsv_chans[i][0];
- ln = rsv_chans[i][1];
- clear_bits(off, ln, cc->edma_unused);
- }
- }
-
- /* Set the reserved slots in inuse list */
- rsv_slots = info->rsv->rsv_slots;
- if (rsv_slots) {
- for (i = 0; rsv_slots[i][0] != -1; i++) {
- off = rsv_slots[i][0];
- ln = rsv_slots[i][1];
- set_bits(off, ln, cc->edma_inuse);
- }
- }
- }
-
- /* Clear the xbar mapped channels in unused list */
- xbar_chans = info->xbar_chans;
- if (xbar_chans) {
- for (i = 0; xbar_chans[i][1] != -1; i++) {
- off = xbar_chans[i][1];
- clear_bits(off, 1, cc->edma_unused);
- }
- }
-
- irq = platform_get_irq_byname(pdev, "edma3_ccint");
- if (irq < 0 && node)
- irq = irq_of_parse_and_map(node, 0);
-
- if (irq >= 0) {
- irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint\n",
- dev_name(dev));
- ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
- cc);
- if (ret) {
- dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
- return ret;
- }
- }
-
- irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
- if (irq < 0 && node)
- irq = irq_of_parse_and_map(node, 2);
-
- if (irq >= 0) {
- irq_name = devm_kasprintf(dev, GFP_KERNEL,
- "%s_ccerrint\n",
- dev_name(dev));
- ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
- cc);
- if (ret) {
- dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
- return ret;
- }
- }
-
- for (i = 0; i < cc->num_channels; i++)
- map_dmach_queue(cc, i, info->default_queue);
-
- queue_priority_mapping = info->queue_priority_mapping;
-
- /* Event queue priority mapping */
- for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(cc, queue_priority_mapping[i][0],
- queue_priority_mapping[i][1]);
-
- /* Map the channel to param entry if channel mapping logic exist */
- if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(cc);
-
- for (i = 0; i < cc->num_region; i++) {
- edma_write_array2(cc, EDMA_DRAE, i, 0, 0x0);
- edma_write_array2(cc, EDMA_DRAE, i, 1, 0x0);
- edma_write_array(cc, EDMA_QRAE, i, 0x0);
- }
- cc->info = info;
- arch_num_cc++;
-
- edma_dev_info.id = dev_id;
-
- platform_device_register_full(&edma_dev_info);
-
- return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int edma_pm_resume(struct device *dev)
-{
- struct edma *cc = dev_get_drvdata(dev);
- int i;
- s8 (*queue_priority_mapping)[2];
-
- queue_priority_mapping = cc->info->queue_priority_mapping;
-
- /* Event queue priority mapping */
- for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(cc, queue_priority_mapping[i][0],
- queue_priority_mapping[i][1]);
-
- /* Map the channel to param entry if channel mapping logic */
- if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(cc);
-
- for (i = 0; i < cc->num_channels; i++) {
- if (test_bit(i, cc->edma_inuse)) {
- /* ensure access through shadow region 0 */
- edma_or_array2(cc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f));
-
- setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, i),
- cc->intr_data[i].callback,
- cc->intr_data[i].data);
- }
- }
-
- return 0;
-}
-#endif
-
-static const struct dev_pm_ops edma_pm_ops = {
- SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume)
-};
-
-static struct platform_driver edma_driver = {
- .driver = {
- .name = "edma",
- .pm = &edma_pm_ops,
- .of_match_table = edma_of_ids,
- },
- .probe = edma_probe,
-};
-
-static int __init edma_init(void)
-{
- return platform_driver_probe(&edma_driver, edma_probe);
-}
-arch_initcall(edma_init);
-
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 07d2e100caab..e0b6736db984 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -90,7 +90,6 @@ config ARCH_OMAP2PLUS
select OMAP_GPMC
select PINCTRL
select SOC_BUS
- select TI_PRIV_EDMA
select OMAP_IRQCHIP
help
Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 2fdfc5ac879f..b5911f3e1636 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -486,7 +486,6 @@ config TI_EDMA
depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
- select TI_PRIV_EDMA
default n
help
Enable support for the TI EDMA controller. This DMA
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index fc91ab9dd1bb..cdde9a69cc59 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -26,12 +26,92 @@
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
#include <linux/platform_data/edma.h>
#include "dmaengine.h"
#include "virt-dma.h"
+/* Offsets matching "struct edmacc_param" */
+#define PARM_OPT 0x00
+#define PARM_SRC 0x04
+#define PARM_A_B_CNT 0x08
+#define PARM_DST 0x0c
+#define PARM_SRC_DST_BIDX 0x10
+#define PARM_LINK_BCNTRLD 0x14
+#define PARM_SRC_DST_CIDX 0x18
+#define PARM_CCNT 0x1c
+
+#define PARM_SIZE 0x20
+
+/* Offsets for EDMA CC global channel registers and their shadows */
+#define SH_ER 0x00 /* 64 bits */
+#define SH_ECR 0x08 /* 64 bits */
+#define SH_ESR 0x10 /* 64 bits */
+#define SH_CER 0x18 /* 64 bits */
+#define SH_EER 0x20 /* 64 bits */
+#define SH_EECR 0x28 /* 64 bits */
+#define SH_EESR 0x30 /* 64 bits */
+#define SH_SER 0x38 /* 64 bits */
+#define SH_SECR 0x40 /* 64 bits */
+#define SH_IER 0x50 /* 64 bits */
+#define SH_IECR 0x58 /* 64 bits */
+#define SH_IESR 0x60 /* 64 bits */
+#define SH_IPR 0x68 /* 64 bits */
+#define SH_ICR 0x70 /* 64 bits */
+#define SH_IEVAL 0x78
+#define SH_QER 0x80
+#define SH_QEER 0x84
+#define SH_QEECR 0x88
+#define SH_QEESR 0x8c
+#define SH_QSER 0x90
+#define SH_QSECR 0x94
+#define SH_SIZE 0x200
+
+/* Offsets for EDMA CC global registers */
+#define EDMA_REV 0x0000
+#define EDMA_CCCFG 0x0004
+#define EDMA_QCHMAP 0x0200 /* 8 registers */
+#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
+#define EDMA_QDMAQNUM 0x0260
+#define EDMA_QUETCMAP 0x0280
+#define EDMA_QUEPRI 0x0284
+#define EDMA_EMR 0x0300 /* 64 bits */
+#define EDMA_EMCR 0x0308 /* 64 bits */
+#define EDMA_QEMR 0x0310
+#define EDMA_QEMCR 0x0314
+#define EDMA_CCERR 0x0318
+#define EDMA_CCERRCLR 0x031c
+#define EDMA_EEVAL 0x0320
+#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
+#define EDMA_QRAE 0x0380 /* 4 registers */
+#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
+#define EDMA_QSTAT 0x0600 /* 2 registers */
+#define EDMA_QWMTHRA 0x0620
+#define EDMA_QWMTHRB 0x0624
+#define EDMA_CCSTAT 0x0640
+
+#define EDMA_M 0x1000 /* global channel registers */
+#define EDMA_ECR 0x1008
+#define EDMA_ECRH 0x100C
+#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
+#define EDMA_PARM 0x4000 /* 128 param entries */
+
+#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
+
+#define EDMA_DCHMAP 0x0100 /* 64 registers */
+
+/* CCCFG register */
+#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
+#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
+#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
+#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
+#define CHMAP_EXIST BIT(24)
+
/*
* This will go away when the private EDMA API is folded
* into this driver and the platform device(s) are
@@ -60,6 +140,47 @@
#define EDMA_MAX_SLOTS MAX_NR_SG
#define EDMA_DESCRIPTORS 16
+#define EDMA_MAX_PARAMENTRY 512
+
+#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY 1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
+
+#define EDMA_MAX_CC 2
+
+/* PaRAM slots are laid out like this */
+struct edmacc_param {
+ u32 opt;
+ u32 src;
+ u32 a_b_cnt;
+ u32 dst;
+ u32 src_dst_bidx;
+ u32 link_bcntrld;
+ u32 src_dst_cidx;
+ u32 ccnt;
+} __packed;
+
+/* fields in edmacc_param.opt */
+#define SAM BIT(0)
+#define DAM BIT(1)
+#define SYNCDIM BIT(2)
+#define STATIC BIT(3)
+#define EDMA_FWID (0x07 << 8)
+#define TCCMODE BIT(11)
+#define EDMA_TCC(t) ((t) << 12)
+#define TCINTEN BIT(20)
+#define ITCINTEN BIT(21)
+#define TCCHEN BIT(22)
+#define ITCCHEN BIT(23)
+
+/*ch_status paramater of callback function possible values*/
+#define EDMA_DMA_COMPLETE 1
+#define EDMA_DMA_CC_ERROR 2
+#define EDMA_DMA_TC1_ERROR 3
+#define EDMA_DMA_TC2_ERROR 4
+
struct edma_pset {
u32 len;
dma_addr_t addr;
@@ -119,14 +240,905 @@ struct edma_chan {
};
struct edma_cc {
- struct edma *cc;
- int ctlr;
+ struct device *dev;
+ struct edma_soc_info *info;
+ void __iomem *base;
+ int id;
+
+ /* eDMA3 resource information */
+ unsigned num_channels;
+ unsigned num_region;
+ unsigned num_slots;
+ unsigned num_tc;
+ enum dma_event_q default_queue;
+
+ bool unused_chan_list_done;
+ /* The edma_inuse bit for each PaRAM slot is clear unless the
+ * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+ */
+ DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+
+ /* The edma_unused bit for each channel is clear unless
+ * it is not being used on this platform. It uses a bit
+ * of SOC-specific initialization code.
+ */
+ DECLARE_BITMAP(edma_unused, EDMA_CHANS);
+
+ struct dma_interrupt_data {
+ void (*callback)(unsigned channel, unsigned short ch_status,
+ void *data);
+ void *data;
+ } intr_data[EDMA_CHANS];
+
struct dma_device dma_slave;
struct edma_chan slave_chans[EDMA_CHANS];
- int num_slave_chans;
int dummy_slot;
};
+/* dummy param set used to (re)initialize parameter RAM slots */
+static const struct edmacc_param dummy_paramset = {
+ .link_bcntrld = 0xffff,
+ .ccnt = 1,
+};
+
+static const struct of_device_id edma_of_ids[] = {
+ { .compatible = "ti,edma3", },
+ {}
+};
+
+static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
+{
+ return (unsigned int)__raw_readl(ecc->base + offset);
+}
+
+static inline void edma_write(struct edma_cc *ecc, int offset, int val)
+{
+ __raw_writel(val, ecc->base + offset);
+}
+static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
+ unsigned or)
+{
+ unsigned val = edma_read(ecc, offset);
+ val &= and;
+ val |= or;
+ edma_write(ecc, offset, val);
+}
+static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
+{
+ unsigned val = edma_read(ecc, offset);
+ val &= and;
+ edma_write(ecc, offset, val);
+}
+static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
+{
+ unsigned val = edma_read(ecc, offset);
+ val |= or;
+ edma_write(ecc, offset, val);
+}
+static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, int i)
+{
+ return edma_read(ecc, offset + (i << 2));
+}
+static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
+ unsigned val)
+{
+ edma_write(ecc, offset + (i << 2), val);
+}
+static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
+ unsigned and, unsigned or)
+{
+ edma_modify(ecc, offset + (i << 2), and, or);
+}
+static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, unsigned or)
+{
+ edma_or(ecc, offset + (i << 2), or);
+}
+static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
+ unsigned or)
+{
+ edma_or(ecc, offset + ((i*2 + j) << 2), or);
+}
+static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, int j,
+ unsigned val)
+{
+ edma_write(ecc, offset + ((i*2 + j) << 2), val);
+}
+static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
+{
+ return edma_read(ecc, EDMA_SHADOW0 + offset);
+}
+static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, int offset,
+ int i)
+{
+ return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
+}
+static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, unsigned val)
+{
+ edma_write(ecc, EDMA_SHADOW0 + offset, val);
+}
+static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, int i,
+ unsigned val)
+{
+ edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
+}
+static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset,
+ int param_no)
+{
+ return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
+}
+static inline void edma_parm_write(struct edma_cc *ecc, int offset, int param_no,
+ unsigned val)
+{
+ edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
+}
+static inline void edma_parm_modify(struct edma_cc *ecc, int offset, int param_no,
+ unsigned and, unsigned or)
+{
+ edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
+}
+static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no,
+ unsigned and)
+{
+ edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
+}
+static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no,
+ unsigned or)
+{
+ edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
+}
+
+static inline void set_bits(int offset, int len, unsigned long *p)
+{
+ for (; len > 0; len--)
+ set_bit(offset + (len - 1), p);
+}
+
+static inline void clear_bits(int offset, int len, unsigned long *p)
+{
+ for (; len > 0; len--)
+ clear_bit(offset + (len - 1), p);
+}
+
+static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no,
+ enum dma_event_q queue_no)
+{
+ int bit = (ch_no & 0x7) * 4;
+
+ /* default to low priority queue */
+ if (queue_no == EVENTQ_DEFAULT)
+ queue_no = ecc->default_queue;
+
+ queue_no &= 7;
+ edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3),
+ ~(0x7 << bit), queue_no << bit);
+}
+
+static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
+ int priority)
+{
+ int bit = queue_no * 4;
+ edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
+}
+
+static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc)
+{
+ int i;
+ for (i = 0; i < ecc->num_channels; i++)
+ edma_write_array(ecc, EDMA_DCHMAP , i , (i << 5));
+}
+
+static int prepare_unused_channel_list(struct device *dev, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct edma_cc *ecc = data;
+ int i, count;
+ struct of_phandle_args dma_spec;
+
+ if (dev->of_node) {
+ struct platform_device *dma_pdev;
+
+ count = of_property_count_strings(dev->of_node, "dma-names");
+ if (count < 0)
+ return 0;
+ for (i = 0; i < count; i++) {
+
+ if (of_parse_phandle_with_args(dev->of_node, "dmas",
+ "#dma-cells", i,
+ &dma_spec))
+ continue;
+
+ if (!of_match_node(edma_of_ids, dma_spec.np)) {
+ of_node_put(dma_spec.np);
+ continue;
+ }
+
+ dma_pdev = of_find_device_by_node(dma_spec.np);
+ if (&dma_pdev->dev != ecc->dev)
+ continue;
+
+ clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
+ ecc->edma_unused);
+ of_node_put(dma_spec.np);
+ }
+ return 0;
+ }
+
+ /* For non-OF case */
+ for (i = 0; i < pdev->num_resources; i++) {
+ struct resource *res = &pdev->resource[i];
+
+ if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
+ clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
+ ecc->edma_unused);
+ }
+ }
+
+ return 0;
+}
+
+static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data)
+{
+ lch = EDMA_CHAN_SLOT(lch);
+
+ if (!callback)
+ edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
+ BIT(lch & 0x1f));
+
+ ecc->intr_data[lch].callback = callback;
+ ecc->intr_data[lch].data = data;
+
+ if (callback) {
+ edma_shadow0_write_array(ecc, SH_ICR, lch >> 5,
+ BIT(lch & 0x1f));
+ edma_shadow0_write_array(ecc, SH_IESR, lch >> 5,
+ BIT(lch & 0x1f));
+ }
+}
+
+/*
+ * paRAM management functions
+ */
+
+/**
+ * edma_write_slot - write parameter RAM data for slot
+ * @ecc: pointer to edma_cc struct
+ * @slot: number of parameter RAM slot being modified
+ * @param: data to be written into parameter RAM slot
+ *
+ * Use this to assign all parameters of a transfer at once. This
+ * allows more efficient setup of transfers than issuing multiple
+ * calls to set up those parameters in small pieces, and provides
+ * complete control over all transfer options.
+ */
+static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
+ const struct edmacc_param *param)
+{
+ slot = EDMA_CHAN_SLOT(slot);
+ if (slot >= ecc->num_slots)
+ return;
+ memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
+}
+
+/**
+ * edma_read_slot - read parameter RAM data from slot
+ * @ecc: pointer to edma_cc struct
+ * @slot: number of parameter RAM slot being copied
+ * @param: where to store copy of parameter RAM data
+ *
+ * Use this to read data from a parameter RAM slot, perhaps to
+ * save them as a template for later reuse.
+ */
+static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
+ struct edmacc_param *param)
+{
+ slot = EDMA_CHAN_SLOT(slot);
+ if (slot >= ecc->num_slots)
+ return;
+ memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
+}
+
+/**
+ * edma_alloc_slot - allocate DMA parameter RAM
+ * @ecc: pointer to edma_cc struct
+ * @slot: specific slot to allocate; negative for "any unused slot"
+ *
+ * This allocates a parameter RAM slot, initializing it to hold a
+ * dummy transfer. Slots allocated using this routine have not been
+ * mapped to a hardware DMA channel, and will normally be used by
+ * linking to them from a slot associated with a DMA channel.
+ *
+ * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
+ * slots may be allocated on behalf of DSP firmware.
+ *
+ * Returns the number of the slot, else negative errno.
+ */
+static int edma_alloc_slot(struct edma_cc *ecc, int slot)
+{
+ if (slot > 0)
+ slot = EDMA_CHAN_SLOT(slot);
+ if (slot < 0) {
+ slot = ecc->num_channels;
+ for (;;) {
+ slot = find_next_zero_bit(ecc->edma_inuse,
+ ecc->num_slots,
+ slot);
+ if (slot == ecc->num_slots)
+ return -ENOMEM;
+ if (!test_and_set_bit(slot, ecc->edma_inuse))
+ break;
+ }
+ } else if (slot < ecc->num_channels || slot >= ecc->num_slots) {
+ return -EINVAL;
+ } else if (test_and_set_bit(slot, ecc->edma_inuse)) {
+ return -EBUSY;
+ }
+
+ edma_write_slot(ecc, slot, &dummy_paramset);
+
+ return EDMA_CTLR_CHAN(ecc->id, slot);
+}
+
+/**
+ * edma_free_slot - deallocate DMA parameter RAM
+ * @ecc: pointer to edma_cc struct
+ * @slot: parameter RAM slot returned from edma_alloc_slot()
+ *
+ * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
+ * Callers are responsible for ensuring the slot is inactive, and will
+ * not be activated.
+ */
+static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
+{
+
+ slot = EDMA_CHAN_SLOT(slot);
+ if (slot < ecc->num_channels || slot >= ecc->num_slots)
+ return;
+
+ edma_write_slot(ecc, slot, &dummy_paramset);
+ clear_bit(slot, ecc->edma_inuse);
+}
+
+/**
+ * edma_link - link one parameter RAM slot to another
+ * @ecc: pointer to edma_cc struct
+ * @from: parameter RAM slot originating the link
+ * @to: parameter RAM slot which is the link target
+ *
+ * The originating slot should not be part of any active DMA transfer.
+ */
+static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
+{
+ from = EDMA_CHAN_SLOT(from);
+ to = EDMA_CHAN_SLOT(to);
+ if (from >= ecc->num_slots || to >= ecc->num_slots)
+ return;
+
+ edma_parm_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ PARM_OFFSET(to));
+}
+
+/**
+ * edma_get_position - returns the current transfer point
+ * @ecc: pointer to edma_cc struct
+ * @slot: parameter RAM slot being examined
+ * @dst: true selects the dest position, false the source
+ *
+ * Returns the position of the current active slot
+ */
+static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
+ bool dst)
+{
+ u32 offs;
+
+ slot = EDMA_CHAN_SLOT(slot);
+ offs = PARM_OFFSET(slot);
+ offs += dst ? PARM_DST : PARM_SRC;
+
+ return edma_read(ecc, offs);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * edma_start - start dma on a channel
+ * @ecc: pointer to edma_cc struct
+ * @channel: channel being activated
+ *
+ * Channels with event associations will be triggered by their hardware
+ * events, and channels without such associations will be triggered by
+ * software. (At this writing there is no interface for using software
+ * triggers except with channels that don't support hardware triggers.)
+ *
+ * Returns zero on success, else negative errno.
+ */
+static int edma_start(struct edma_cc *ecc, unsigned channel)
+{
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < ecc->num_channels) {
+ int j = channel >> 5;
+ unsigned int mask = BIT(channel & 0x1f);
+
+ /* EDMA channels without event association */
+ if (test_bit(channel, ecc->edma_unused)) {
+ pr_debug("EDMA: ESR%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_ESR, j));
+ edma_shadow0_write_array(ecc, SH_ESR, j, mask);
+ return 0;
+ }
+
+ /* EDMA channel with event association */
+ pr_debug("EDMA: ER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_ER, j));
+ /* Clear any pending event or error */
+ edma_write_array(ecc, EDMA_ECR, j, mask);
+ edma_write_array(ecc, EDMA_EMCR, j, mask);
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR, j, mask);
+ edma_shadow0_write_array(ecc, SH_EESR, j, mask);
+ pr_debug("EDMA: EER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_EER, j));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+/**
+ * edma_stop - stops dma on the channel passed
+ * @ecc: pointer to edma_cc struct
+ * @channel: channel being deactivated
+ *
+ * When @lch is a channel, any active transfer is paused and
+ * all pending hardware events are cleared. The current transfer
+ * may not be resumed, and the channel's Parameter RAM should be
+ * reinitialized before being reused.
+ */
+static void edma_stop(struct edma_cc *ecc, unsigned channel)
+{
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < ecc->num_channels) {
+ int j = channel >> 5;
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ecc, SH_EECR, j, mask);
+ edma_shadow0_write_array(ecc, SH_ECR, j, mask);
+ edma_shadow0_write_array(ecc, SH_SECR, j, mask);
+ edma_write_array(ecc, EDMA_EMCR, j, mask);
+
+ /* clear possibly pending completion interrupt */
+ edma_shadow0_write_array(ecc, SH_ICR, j, mask);
+
+ pr_debug("EDMA: EER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_EER, j));
+
+ /* REVISIT: consider guarding against inappropriate event
+ * chaining by overwriting with dummy_paramset.
+ */
+ }
+}
+
+/**
+ * edma_pause - pause dma on a channel
+ * @ecc: pointer to edma_cc struct
+ * @channel: on which edma_start() has been called
+ *
+ * This temporarily disables EDMA hardware events on the specified channel,
+ * preventing them from triggering new transfers on its behalf
+ */
+static void edma_pause(struct edma_cc *ecc, unsigned channel)
+{
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < ecc->num_channels) {
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ecc, SH_EECR, channel >> 5, mask);
+ }
+}
+
+/**
+ * edma_resume - resumes dma on a paused channel
+ * @ecc: pointer to edma_cc struct
+ * @channel: on which edma_pause() has been called
+ *
+ * This re-enables EDMA hardware events on the specified channel.
+ */
+static void edma_resume(struct edma_cc *ecc, unsigned channel)
+{
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < ecc->num_channels) {
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ecc, SH_EESR, channel >> 5, mask);
+ }
+}
+
+static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
+{
+ unsigned int mask;
+
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+ mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
+
+ pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
+ edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
+ return 0;
+}
+
+/******************************************************************************
+ *
+ * It cleans ParamEntry qand bring back EDMA to initial state if media has
+ * been removed before EDMA has finished.It is usedful for removable media.
+ * Arguments:
+ * ch_no - channel no
+ *
+ * Return: zero on success, or corresponding error no on failure
+ *
+ * FIXME this should not be needed ... edma_stop() should suffice.
+ *
+ *****************************************************************************/
+
+static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
+{
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < ecc->num_channels) {
+ int j = (channel >> 5);
+ unsigned int mask = BIT(channel & 0x1f);
+
+ pr_debug("EDMA: EMR%d %08x\n", j,
+ edma_read_array(ecc, EDMA_EMR, j));
+ edma_shadow0_write_array(ecc, SH_ECR, j, mask);
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ecc, EDMA_EMCR, j, mask);
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR, j, mask);
+ edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
+ }
+}
+
+/**
+ * edma_alloc_channel - allocate DMA channel and paired parameter RAM
+ * @ecc: pointer to edma_cc struct
+ * @channel: specific channel to allocate; negative for "any unmapped channel"
+ * @callback: optional; to be issued on DMA completion or errors
+ * @data: passed to callback
+ * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
+ * Controller (TC) executes requests using this channel. Use
+ * EVENTQ_DEFAULT unless you really need a high priority queue.
+ *
+ * This allocates a DMA channel and its associated parameter RAM slot.
+ * The parameter RAM is initialized to hold a dummy transfer.
+ *
+ * Normal use is to pass a specific channel number as @channel, to make
+ * use of hardware events mapped to that channel. When the channel will
+ * be used only for software triggering or event chaining, channels not
+ * mapped to hardware events (or mapped to unused events) are preferable.
+ *
+ * DMA transfers start from a channel using edma_start(), or by
+ * chaining. When the transfer described in that channel's parameter RAM
+ * slot completes, that slot's data may be reloaded through a link.
+ *
+ * DMA errors are only reported to the @callback associated with the
+ * channel driving that transfer, but transfer completion callbacks can
+ * be sent to another channel under control of the TCC field in
+ * the option word of the transfer's parameter RAM set. Drivers must not
+ * use DMA transfer completion callbacks for channels they did not allocate.
+ * (The same applies to TCC codes used in transfer chaining.)
+ *
+ * Returns the number of the channel, else negative errno.
+ */
+static int edma_alloc_channel(struct edma_cc *ecc, int channel,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data,
+ enum dma_event_q eventq_no)
+{
+ unsigned done = 0;
+ int ret = 0;
+
+ if (!ecc->unused_chan_list_done) {
+ /*
+ * Scan all the platform devices to find out the EDMA channels
+ * used and clear them in the unused list, making the rest
+ * available for ARM usage.
+ */
+ ret = bus_for_each_dev(&platform_bus_type, NULL, ecc,
+ prepare_unused_channel_list);
+ if (ret < 0)
+ return ret;
+
+ ecc->unused_chan_list_done = true;
+ }
+
+ if (channel >= 0) {
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n",
+ __func__, ecc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+ }
+
+ if (channel < 0) {
+ channel = 0;
+ for (;;) {
+ channel = find_next_bit(ecc->edma_unused,
+ ecc->num_channels, channel);
+ if (channel == ecc->num_channels)
+ break;
+ if (!test_and_set_bit(channel, ecc->edma_inuse)) {
+ done = 1;
+ break;
+ }
+ channel++;
+ }
+ if (!done)
+ return -ENOMEM;
+ } else if (channel >= ecc->num_channels) {
+ return -EINVAL;
+ } else if (test_and_set_bit(channel, ecc->edma_inuse)) {
+ return -EBUSY;
+ }
+
+ /* ensure access through shadow region 0 */
+ edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+
+ /* ensure no events are pending */
+ edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));
+ edma_write_slot(ecc, channel, &dummy_paramset);
+
+ if (callback)
+ edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel),
+ callback, data);
+
+ edma_map_dmach_to_queue(ecc, channel, eventq_no);
+
+ return EDMA_CTLR_CHAN(ecc->id, channel);
+}
+
+
+/**
+ * edma_free_channel - deallocate DMA channel
+ * @ecc: pointer to edma_cc struct
+ * @channel: dma channel returned from edma_alloc_channel()
+ *
+ * This deallocates the DMA channel and associated parameter RAM slot
+ * allocated by edma_alloc_channel().
+ *
+ * Callers are responsible for ensuring the channel is inactive, and
+ * will not be reactivated by linking, chaining, or software calls to
+ * edma_start().
+ */
+static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
+{
+
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= ecc->num_channels)
+ return;
+
+ edma_setup_interrupt(ecc, channel, NULL, NULL);
+ /* REVISIT should probably take out of shadow region 0 */
+
+ memcpy_toio(ecc->base + PARM_OFFSET(channel), &dummy_paramset,
+ PARM_SIZE);
+ clear_bit(channel, ecc->edma_inuse);
+}
+
+/*
+ * edma_assign_channel_eventq - move given channel to desired eventq
+ * Arguments:
+ * channel - channel number
+ * eventq_no - queue to move the channel
+ *
+ * Can be used to move a channel to a selected event queue.
+ */
+static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
+ enum dma_event_q eventq_no)
+{
+ if (ecc->id != EDMA_CTLR(channel)) {
+ dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ ecc->id, EDMA_CTLR(channel));
+ return;
+ }
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= ecc->num_channels)
+ return;
+
+ /* default to low priority queue */
+ if (eventq_no == EVENTQ_DEFAULT)
+ eventq_no = ecc->default_queue;
+ if (eventq_no >= ecc->num_tc)
+ return;
+
+ edma_map_dmach_to_queue(ecc, channel, eventq_no);
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *data)
+{
+ struct edma_cc *ecc = data;
+ int ctlr;
+ u32 sh_ier;
+ u32 sh_ipr;
+ u32 bank;
+
+ ctlr = ecc->id;
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(ecc->dev, "dma_irq_handler\n");
+
+ sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
+ if (!sh_ipr) {
+ sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
+ if (!sh_ipr)
+ return IRQ_NONE;
+ sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
+ bank = 1;
+ } else {
+ sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
+ bank = 0;
+ }
+
+ do {
+ u32 slot;
+ u32 channel;
+
+ dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr);
+
+ slot = __ffs(sh_ipr);
+ sh_ipr &= ~(BIT(slot));
+
+ if (sh_ier & BIT(slot)) {
+ channel = (bank << 5) | slot;
+ /* Clear the corresponding IPR bits */
+ edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
+ if (ecc->intr_data[channel].callback)
+ ecc->intr_data[channel].callback(
+ EDMA_CTLR_CHAN(ctlr, channel),
+ EDMA_DMA_COMPLETE,
+ ecc->intr_data[channel].data);
+ }
+ } while (sh_ipr);
+
+ edma_shadow0_write(ecc, SH_IEVAL, 1);
+ return IRQ_HANDLED;
+}
+
+/******************************************************************************
+ *
+ * DMA error interrupt handler
+ *
+ *****************************************************************************/
+static irqreturn_t dma_ccerr_handler(int irq, void *data)
+{
+ struct edma_cc *ecc = data;
+ int i;
+ int ctlr;
+ unsigned int cnt = 0;
+
+ ctlr = ecc->id;
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(ecc->dev, "dma_ccerr_handler\n");
+
+ if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
+ (edma_read(ecc, EDMA_QEMR) == 0) &&
+ (edma_read(ecc, EDMA_CCERR) == 0))
+ return IRQ_NONE;
+
+ while (1) {
+ int j = -1;
+ if (edma_read_array(ecc, EDMA_EMR, 0))
+ j = 0;
+ else if (edma_read_array(ecc, EDMA_EMR, 1))
+ j = 1;
+ if (j >= 0) {
+ dev_dbg(ecc->dev, "EMR%d %08x\n", j,
+ edma_read_array(ecc, EDMA_EMR, j));
+ for (i = 0; i < 32; i++) {
+ int k = (j << 5) + i;
+ if (edma_read_array(ecc, EDMA_EMR, j) &
+ BIT(i)) {
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ecc, EDMA_EMCR, j,
+ BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR,
+ j, BIT(i));
+ if (ecc->intr_data[k].callback) {
+ ecc->intr_data[k].callback(
+ EDMA_CTLR_CHAN(ctlr, k),
+ EDMA_DMA_CC_ERROR,
+ ecc->intr_data[k].data);
+ }
+ }
+ }
+ } else if (edma_read(ecc, EDMA_QEMR)) {
+ dev_dbg(ecc->dev, "QEMR %02x\n",
+ edma_read(ecc, EDMA_QEMR));
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ecc, EDMA_QEMCR, BIT(i));
+ edma_shadow0_write(ecc, SH_QSECR,
+ BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ } else if (edma_read(ecc, EDMA_CCERR)) {
+ dev_dbg(ecc->dev, "CCERR %08x\n",
+ edma_read(ecc, EDMA_CCERR));
+ /* FIXME: CCERR.BIT(16) ignored! much better
+ * to just write CCERRCLR with CCERR value...
+ */
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ecc, EDMA_CCERRCLR, BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ }
+ if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
+ (edma_read(ecc, EDMA_QEMR) == 0) &&
+ (edma_read(ecc, EDMA_CCERR) == 0))
+ break;
+ cnt++;
+ if (cnt > 10)
+ break;
+ }
+ edma_write(ecc, EDMA_EEVAL, 1);
+ return IRQ_HANDLED;
+}
+
static inline struct edma_cc *to_edma_cc(struct dma_device *d)
{
return container_of(d, struct edma_cc, dma_slave);
@@ -151,7 +1163,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc)
/* Dispatch a queued descriptor to the controller (caller holds lock) */
static void edma_execute(struct edma_chan *echan)
{
- struct edma *cc = echan->ecc->cc;
+ struct edma_cc *ecc = echan->ecc;
struct virt_dma_desc *vdesc;
struct edma_desc *edesc;
struct device *dev = echan->vchan.chan.device->dev;
@@ -176,7 +1188,7 @@ static void edma_execute(struct edma_chan *echan)
/* Write descriptor PaRAM set(s) */
for (i = 0; i < nslots; i++) {
j = i + edesc->processed;
- edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param);
+ edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
edesc->sg_len += edesc->pset[j].len;
dev_vdbg(echan->vchan.chan.device->dev,
"\n pset[%d]:\n"
@@ -201,7 +1213,7 @@ static void edma_execute(struct edma_chan *echan)
edesc->pset[j].param.link_bcntrld);
/* Link to the previous slot if not the last set */
if (i != (nslots - 1))
- edma_link(cc, echan->slot[i], echan->slot[i+1]);
+ edma_link(ecc, echan->slot[i], echan->slot[i+1]);
}
edesc->processed += nslots;
@@ -213,9 +1225,9 @@ static void edma_execute(struct edma_chan *echan)
*/
if (edesc->processed == edesc->pset_nr) {
if (edesc->cyclic)
- edma_link(cc, echan->slot[nslots-1], echan->slot[1]);
+ edma_link(ecc, echan->slot[nslots-1], echan->slot[1]);
else
- edma_link(cc, echan->slot[nslots-1],
+ edma_link(ecc, echan->slot[nslots-1],
echan->ecc->dummy_slot);
}
@@ -226,19 +1238,19 @@ static void edma_execute(struct edma_chan *echan)
* transfers of MAX_NR_SG
*/
dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
- edma_clean_channel(cc, echan->ch_num);
- edma_stop(cc, echan->ch_num);
- edma_start(cc, echan->ch_num);
- edma_trigger_channel(cc, echan->ch_num);
+ edma_clean_channel(ecc, echan->ch_num);
+ edma_stop(ecc, echan->ch_num);
+ edma_start(ecc, echan->ch_num);
+ edma_trigger_channel(ecc, echan->ch_num);
echan->missed = 0;
} else if (edesc->processed <= MAX_NR_SG) {
dev_dbg(dev, "first transfer starting on channel %d\n",
echan->ch_num);
- edma_start(cc, echan->ch_num);
+ edma_start(ecc, echan->ch_num);
} else {
dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
echan->ch_num, edesc->processed);
- edma_resume(cc, echan->ch_num);
+ edma_resume(ecc, echan->ch_num);
}
}
@@ -256,10 +1268,10 @@ static int edma_terminate_all(struct dma_chan *chan)
* echan->edesc is NULL and exit.)
*/
if (echan->edesc) {
- edma_stop(echan->ecc->cc, echan->ch_num);
+ edma_stop(echan->ecc, echan->ch_num);
/* Move the cyclic channel back to default queue */
if (echan->edesc->cyclic)
- edma_assign_channel_eventq(echan->ecc->cc,
+ edma_assign_channel_eventq(echan->ecc,
echan->ch_num,
EVENTQ_DEFAULT);
/*
@@ -298,7 +1310,7 @@ static int edma_dma_pause(struct dma_chan *chan)
if (!echan->edesc)
return -EINVAL;
- edma_pause(echan->ecc->cc, echan->ch_num);
+ edma_pause(echan->ecc, echan->ch_num);
return 0;
}
@@ -306,7 +1318,7 @@ static int edma_dma_resume(struct dma_chan *chan)
{
struct edma_chan *echan = to_edma_chan(chan);
- edma_resume(echan->ecc->cc, echan->ch_num);
+ edma_resume(echan->ecc, echan->ch_num);
return 0;
}
@@ -488,7 +1500,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
for (i = 0; i < nslots; i++) {
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -643,7 +1655,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
/* Allocate a PaRAM slot, if needed */
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -704,7 +1716,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
}
/* Place the cyclic channel to highest priority queue */
- edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0);
+ edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_0);
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}
@@ -712,7 +1724,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
{
struct edma_chan *echan = data;
- struct edma *cc = echan->ecc->cc;
+ struct edma_cc *ecc = echan->ecc;
struct device *dev = echan->vchan.chan.device->dev;
struct edma_desc *edesc;
struct edmacc_param p;
@@ -729,13 +1741,13 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
} else if (edesc->processed == edesc->pset_nr) {
dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
edesc->residue = 0;
- edma_stop(cc, echan->ch_num);
+ edma_stop(ecc, echan->ch_num);
vchan_cookie_complete(&edesc->vdesc);
echan->edesc = NULL;
} else {
dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
- edma_pause(cc, echan->ch_num);
+ edma_pause(ecc, echan->ch_num);
/* Update statistics for tx_status */
edesc->residue -= edesc->sg_len;
@@ -746,7 +1758,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
}
break;
case EDMA_DMA_CC_ERROR:
- edma_read_slot(cc, echan->slot[0], &p);
+ edma_read_slot(ecc, echan->slot[0], &p);
/*
* Issue later based on missed flag which will be sure
@@ -769,10 +1781,10 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
* missed, so its safe to issue it here.
*/
dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
- edma_clean_channel(cc, echan->ch_num);
- edma_stop(cc, echan->ch_num);
- edma_start(cc, echan->ch_num);
- edma_trigger_channel(cc, echan->ch_num);
+ edma_clean_channel(ecc, echan->ch_num);
+ edma_stop(ecc, echan->ch_num);
+ edma_start(ecc, echan->ch_num);
+ edma_trigger_channel(ecc, echan->ch_num);
}
break;
default:
@@ -791,7 +1803,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
int a_ch_num;
LIST_HEAD(descs);
- a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num,
+ a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num,
edma_callback, echan, EVENTQ_DEFAULT);
if (a_ch_num < 0) {
@@ -816,7 +1828,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
return 0;
err_wrong_chan:
- edma_free_channel(echan->ecc->cc, a_ch_num);
+ edma_free_channel(echan->ecc, a_ch_num);
err_no_chan:
return ret;
}
@@ -829,21 +1841,21 @@ static void edma_free_chan_resources(struct dma_chan *chan)
int i;
/* Terminate transfers */
- edma_stop(echan->ecc->cc, echan->ch_num);
+ edma_stop(echan->ecc, echan->ch_num);
vchan_free_chan_resources(&echan->vchan);
/* Free EDMA PaRAM slots */
for (i = 1; i < EDMA_MAX_SLOTS; i++) {
if (echan->slot[i] >= 0) {
- edma_free_slot(echan->ecc->cc, echan->slot[i]);
+ edma_free_slot(echan->ecc, echan->slot[i]);
echan->slot[i] = -1;
}
}
/* Free EDMA channel */
if (echan->alloced) {
- edma_free_channel(echan->ecc->cc, echan->ch_num);
+ edma_free_channel(echan->ecc, echan->ch_num);
echan->alloced = false;
}
@@ -873,7 +1885,7 @@ static u32 edma_residue(struct edma_desc *edesc)
* We always read the dst/src position from the first RamPar
* pset. That's the one which is active now.
*/
- pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0],
+ pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0],
dst);
/*
@@ -943,7 +1955,7 @@ static void __init edma_chan_init(struct edma_cc *ecc,
for (i = 0; i < EDMA_CHANS; i++) {
struct edma_chan *echan = &echans[i];
- echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
+ echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
echan->ecc = ecc;
echan->vchan.desc_free = edma_desc_free;
@@ -991,14 +2003,188 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
INIT_LIST_HEAD(&dma->channels);
}
+static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
+ struct edma_cc *ecc)
+{
+ int i;
+ u32 value, cccfg;
+ s8 (*queue_priority_map)[2];
+
+ /* Decode the eDMA3 configuration from CCCFG register */
+ cccfg = edma_read(ecc, EDMA_CCCFG);
+
+ value = GET_NUM_REGN(cccfg);
+ ecc->num_region = BIT(value);
+
+ value = GET_NUM_DMACH(cccfg);
+ ecc->num_channels = BIT(value + 1);
+
+ value = GET_NUM_PAENTRY(cccfg);
+ ecc->num_slots = BIT(value + 4);
+
+ value = GET_NUM_EVQUE(cccfg);
+ ecc->num_tc = value + 1;
+
+ dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
+ dev_dbg(dev, "num_region: %u\n", ecc->num_region);
+ dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
+ dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
+ dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
+
+ /* Nothing need to be done if queue priority is provided */
+ if (pdata->queue_priority_mapping)
+ return 0;
+
+ /*
+ * Configure TC/queue priority as follows:
+ * Q0 - priority 0
+ * Q1 - priority 1
+ * Q2 - priority 2
+ * ...
+ * The meaning of priority numbers: 0 highest priority, 7 lowest
+ * priority. So Q0 is the highest priority queue and the last queue has
+ * the lowest priority.
+ */
+ queue_priority_map = devm_kzalloc(dev, (ecc->num_tc + 1) * sizeof(s8),
+ GFP_KERNEL);
+ if (!queue_priority_map)
+ return -ENOMEM;
+
+ for (i = 0; i < ecc->num_tc; i++) {
+ queue_priority_map[i][0] = i;
+ queue_priority_map[i][1] = i;
+ }
+ queue_priority_map[i][0] = -1;
+ queue_priority_map[i][1] = -1;
+
+ pdata->queue_priority_mapping = queue_priority_map;
+ /* Default queue has the lowest priority */
+ pdata->default_queue = i - 1;
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF)
+static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
+ size_t sz)
+{
+ const char pname[] = "ti,edma-xbar-event-map";
+ struct resource res;
+ void __iomem *xbar;
+ s16 (*xbar_chans)[2];
+ size_t nelm = sz / sizeof(s16);
+ u32 shift, offset, mux;
+ int ret, i;
+
+ xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
+ if (!xbar_chans)
+ return -ENOMEM;
+
+ ret = of_address_to_resource(dev->of_node, 1, &res);
+ if (ret)
+ return -ENOMEM;
+
+ xbar = devm_ioremap(dev, res.start, resource_size(&res));
+ if (!xbar)
+ return -ENOMEM;
+
+ ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
+ nelm);
+ if (ret)
+ return -EIO;
+
+ /* Invalidate last entry for the other user of this mess */
+ nelm >>= 1;
+ xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
+
+ for (i = 0; i < nelm; i++) {
+ shift = (xbar_chans[i][1] & 0x03) << 3;
+ offset = xbar_chans[i][1] & 0xfffffffc;
+ mux = readl(xbar + offset);
+ mux &= ~(0xff << shift);
+ mux |= xbar_chans[i][0] << shift;
+ writel(mux, (xbar + offset));
+ }
+
+ pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
+ return 0;
+}
+
+static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata)
+{
+ int ret = 0;
+ struct property *prop;
+ size_t sz;
+ struct edma_rsv_info *rsv_info;
+
+ rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
+ if (!rsv_info)
+ return -ENOMEM;
+ pdata->rsv = rsv_info;
+
+ prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz);
+ if (prop)
+ ret = edma_xbar_event_map(dev, pdata, sz);
+
+ return ret;
+}
+
+static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev)
+{
+ struct edma_soc_info *info;
+ int ret;
+
+ info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
+ if (!info)
+ return ERR_PTR(-ENOMEM);
+
+ ret = edma_of_parse_dt(dev, info);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return info;
+}
+#else
+static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev)
+{
+ return ERR_PTR(-ENOSYS);
+}
+#endif
+
static int edma_probe(struct platform_device *pdev)
{
- struct edma_cc *ecc;
- struct device_node *parent_node = pdev->dev.parent->of_node;
- struct platform_device *parent_pdev =
- to_platform_device(pdev->dev.parent);
+ struct edma_soc_info *info = pdev->dev.platform_data;
+ s8 (*queue_priority_mapping)[2];
+ int i, off, ln;
+ const s16 (*rsv_chans)[2];
+ const s16 (*rsv_slots)[2];
+ const s16 (*xbar_chans)[2];
+ int irq;
+ char *irq_name;
+ struct resource *mem;
+ struct device_node *node = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct edma_cc *ecc;
int ret;
+ if (node) {
+ info = edma_setup_info_from_dt(dev);
+ if (IS_ERR(info)) {
+ dev_err(dev, "failed to get DT data\n");
+ return PTR_ERR(info);
+ }
+ }
+
+ if (!info)
+ return -ENODEV;
+
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ dev_err(dev, "pm_runtime_get_sync() failed\n");
+ return ret;
+ }
+
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
@@ -1009,15 +2195,125 @@ static int edma_probe(struct platform_device *pdev)
return -ENOMEM;
}
- ecc->cc = edma_get_data(pdev->dev.parent);
- if (!ecc->cc)
- return -ENODEV;
+ ecc->dev = dev;
+ ecc->id = pdev->id;
+ /* When booting with DT the pdev->id is -1 */
+ if (ecc->id < 0)
+ ecc->id = 0;
+
+
+ mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
+ if (!mem) {
+ dev_dbg(dev, "mem resource not found, using index 0\n");
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem) {
+ dev_err(dev, "no mem resource?\n");
+ return -ENODEV;
+ }
+ }
+ ecc->base = devm_ioremap_resource(dev, mem);
+ if (IS_ERR(ecc->base))
+ return PTR_ERR(ecc->base);
+
+ platform_set_drvdata(pdev, ecc);
+
+ /* Get eDMA3 configuration from IP */
+ ret = edma_setup_from_hw(dev, info, ecc);
+ if (ret)
+ return ret;
+
+ ecc->default_queue = info->default_queue;
+
+ for (i = 0; i < ecc->num_slots; i++)
+ edma_write_slot(ecc, i, &dummy_paramset);
+
+ /* Mark all channels as unused */
+ memset(ecc->edma_unused, 0xff, sizeof(ecc->edma_unused));
+
+ if (info->rsv) {
+ /* Clear the reserved channels in unused list */
+ rsv_chans = info->rsv->rsv_chans;
+ if (rsv_chans) {
+ for (i = 0; rsv_chans[i][0] != -1; i++) {
+ off = rsv_chans[i][0];
+ ln = rsv_chans[i][1];
+ clear_bits(off, ln, ecc->edma_unused);
+ }
+ }
+
+ /* Set the reserved slots in inuse list */
+ rsv_slots = info->rsv->rsv_slots;
+ if (rsv_slots) {
+ for (i = 0; rsv_slots[i][0] != -1; i++) {
+ off = rsv_slots[i][0];
+ ln = rsv_slots[i][1];
+ set_bits(off, ln, ecc->edma_inuse);
+ }
+ }
+ }
- ecc->ctlr = parent_pdev->id;
- if (ecc->ctlr < 0)
- ecc->ctlr = 0;
+ /* Clear the xbar mapped channels in unused list */
+ xbar_chans = info->xbar_chans;
+ if (xbar_chans) {
+ for (i = 0; xbar_chans[i][1] != -1; i++) {
+ off = xbar_chans[i][1];
+ clear_bits(off, 1, ecc->edma_unused);
+ }
+ }
+
+ irq = platform_get_irq_byname(pdev, "edma3_ccint");
+ if (irq < 0 && node)
+ irq = irq_of_parse_and_map(node, 0);
+
+ if (irq >= 0) {
+ irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint\n",
+ dev_name(dev));
+ ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
+ ecc);
+ if (ret) {
+ dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
+ return ret;
+ }
+ }
- ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY);
+ irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
+ if (irq < 0 && node)
+ irq = irq_of_parse_and_map(node, 2);
+
+ if (irq >= 0) {
+ irq_name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s_ccerrint\n",
+ dev_name(dev));
+ ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
+ ecc);
+ if (ret) {
+ dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ecc->num_channels; i++)
+ edma_map_dmach_to_queue(ecc, i, info->default_queue);
+
+ queue_priority_mapping = info->queue_priority_mapping;
+
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
+
+ /* Map the channel to param entry if channel mapping logic exist */
+ if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
+ edma_direct_dmach_to_param_mapping(ecc);
+
+ for (i = 0; i < ecc->num_region; i++) {
+ edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
+ edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
+ edma_write_array(ecc, EDMA_QRAE, i, 0x0);
+ }
+ ecc->info = info;
+
+ ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
return ecc->dummy_slot;
@@ -1036,19 +2332,16 @@ static int edma_probe(struct platform_device *pdev)
if (ret)
goto err_reg1;
- platform_set_drvdata(pdev, ecc);
-
- if (parent_node) {
- of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id,
+ if (node)
+ of_dma_controller_register(node, of_dma_xlate_by_chan_id,
&ecc->dma_slave);
- }
dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
return 0;
err_reg1:
- edma_free_slot(ecc->cc, ecc->dummy_slot);
+ edma_free_slot(ecc, ecc->dummy_slot);
return ret;
}
@@ -1056,12 +2349,11 @@ static int edma_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct edma_cc *ecc = dev_get_drvdata(dev);
- struct device_node *parent_node = pdev->dev.parent->of_node;
- if (parent_node)
- of_dma_controller_free(parent_node);
+ if (pdev->dev.of_node)
+ of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&ecc->dma_slave);
- edma_free_slot(ecc->cc, ecc->dummy_slot);
+ edma_free_slot(ecc, ecc->dummy_slot);
return 0;
}
@@ -1070,7 +2362,8 @@ static struct platform_driver edma_driver = {
.probe = edma_probe,
.remove = edma_remove,
.driver = {
- .name = "edma-dma-engine",
+ .name = "edma",
+ .of_match_table = edma_of_ids,
},
};
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index 466021c03169..6b9d500956e4 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -41,37 +41,6 @@
#ifndef EDMA_H_
#define EDMA_H_
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
- u32 opt;
- u32 src;
- u32 a_b_cnt;
- u32 dst;
- u32 src_dst_bidx;
- u32 link_bcntrld;
- u32 src_dst_cidx;
- u32 ccnt;
-} __packed;
-
-/* fields in edmacc_param.opt */
-#define SAM BIT(0)
-#define DAM BIT(1)
-#define SYNCDIM BIT(2)
-#define STATIC BIT(3)
-#define EDMA_FWID (0x07 << 8)
-#define TCCMODE BIT(11)
-#define EDMA_TCC(t) ((t) << 12)
-#define TCINTEN BIT(20)
-#define ITCINTEN BIT(21)
-#define TCCHEN BIT(22)
-#define ITCCHEN BIT(23)
-
-/*ch_status paramater of callback function possible values*/
-#define EDMA_DMA_COMPLETE 1
-#define EDMA_DMA_CC_ERROR 2
-#define EDMA_DMA_TC1_ERROR 3
-#define EDMA_DMA_TC2_ERROR 4
-
enum dma_event_q {
EVENTQ_0 = 0,
EVENTQ_1 = 1,
@@ -84,49 +53,6 @@ enum dma_event_q {
#define EDMA_CTLR(i) ((i) >> 16)
#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
-#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY 1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-
-#define EDMA_MAX_CC 2
-
-struct edma;
-
-struct edma *edma_get_data(struct device *edma_dev);
-
-/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(struct edma *cc, int channel,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data, enum dma_event_q);
-void edma_free_channel(struct edma *cc, unsigned channel);
-
-/* alloc/free parameter RAM slots */
-int edma_alloc_slot(struct edma *cc, int slot);
-void edma_free_slot(struct edma *cc, unsigned slot);
-
-/* calls that operate on part of a parameter RAM slot */
-dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst);
-void edma_link(struct edma *cc, unsigned from, unsigned to);
-
-/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(struct edma *cc, unsigned slot,
- const struct edmacc_param *params);
-void edma_read_slot(struct edma *cc, unsigned slot,
- struct edmacc_param *params);
-
-/* channel control operations */
-int edma_start(struct edma *cc, unsigned channel);
-void edma_stop(struct edma *cc, unsigned channel);
-void edma_clean_channel(struct edma *cc, unsigned channel);
-void edma_pause(struct edma *cc, unsigned channel);
-void edma_resume(struct edma *cc, unsigned channel);
-int edma_trigger_channel(struct edma *cc, unsigned channel);
-
-void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
- enum dma_event_q eventq_no);
-
struct edma_rsv_info {
const s16 (*rsv_chans)[2];
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 11/21] dmaengine: edma: Allocate memory dynamically for bitmaps and structures
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (9 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 10/21] ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 12/21] dmaengine: edma: Parameter alignment and long line fixes Peter Ujfalusi
` (10 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Instead of using defines to specify the size of different arrays and
bitmaps, allocate the memory for them based on the information we get from
the HW itself.
Since these defines are set based on the worst case, there are devices
where they are not valid.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 62 ++++++++++++++++++++++++++++++------------------------
1 file changed, 34 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index cdde9a69cc59..153869c9e13c 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -113,23 +113,6 @@
#define CHMAP_EXIST BIT(24)
/*
- * This will go away when the private EDMA API is folded
- * into this driver and the platform device(s) are
- * instantiated in the arch code. We can only get away
- * with this simplification because DA8XX may not be built
- * in the same kernel image with other DaVinci parts. This
- * avoids having to sprinkle dmaengine driver platform devices
- * and data throughout all the existing board files.
- */
-#ifdef CONFIG_ARCH_DAVINCI_DA8XX
-#define EDMA_CTLRS 2
-#define EDMA_CHANS 32
-#else
-#define EDMA_CTLRS 1
-#define EDMA_CHANS 64
-#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
-
-/*
* Max of 20 segments per channel to conserve PaRAM slots
* Also note that MAX_NR_SG should be atleast the no.of periods
* that are required for ASoC, otherwise DMA prep calls will
@@ -140,16 +123,12 @@
#define EDMA_MAX_SLOTS MAX_NR_SG
#define EDMA_DESCRIPTORS 16
-#define EDMA_MAX_PARAMENTRY 512
-
#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
#define EDMA_CONT_PARAMS_ANY 1001
#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-#define EDMA_MAX_CC 2
-
/* PaRAM slots are laid out like this */
struct edmacc_param {
u32 opt;
@@ -256,22 +235,22 @@ struct edma_cc {
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+ unsigned long *edma_inuse;
/* The edma_unused bit for each channel is clear unless
* it is not being used on this platform. It uses a bit
* of SOC-specific initialization code.
*/
- DECLARE_BITMAP(edma_unused, EDMA_CHANS);
+ unsigned long *edma_unused;
struct dma_interrupt_data {
void (*callback)(unsigned channel, unsigned short ch_status,
void *data);
void *data;
- } intr_data[EDMA_CHANS];
+ } *intr_data;
struct dma_device dma_slave;
- struct edma_chan slave_chans[EDMA_CHANS];
+ struct edma_chan *slave_chans;
int dummy_slot;
};
@@ -431,6 +410,8 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
struct edma_cc *ecc = data;
+ int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0);
+ int dma_req_max = dma_req_min + ecc->num_channels;
int i, count;
struct of_phandle_args dma_spec;
@@ -466,11 +447,15 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/* For non-OF case */
for (i = 0; i < pdev->num_resources; i++) {
struct resource *res = &pdev->resource[i];
+ int dma_req;
- if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
+ if (!(res->flags & IORESOURCE_DMA))
+ continue;
+
+ dma_req = (int)res->start;
+ if (dma_req >= dma_req_min && dma_req < dma_req_max)
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
ecc->edma_unused);
- }
}
return 0;
@@ -1953,7 +1938,7 @@ static void __init edma_chan_init(struct edma_cc *ecc,
{
int i, j;
- for (i = 0; i < EDMA_CHANS; i++) {
+ for (i = 0; i < ecc->num_channels; i++) {
struct edma_chan *echan = &echans[i];
echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
echan->ecc = ecc;
@@ -2222,6 +2207,27 @@ static int edma_probe(struct platform_device *pdev)
if (ret)
return ret;
+ /* Allocate memory based on the information we got from the IP */
+ ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
+ sizeof(*ecc->slave_chans), GFP_KERNEL);
+ if (!ecc->slave_chans)
+ return -ENOMEM;
+
+ ecc->intr_data = devm_kcalloc(dev, ecc->num_channels,
+ sizeof(*ecc->intr_data), GFP_KERNEL);
+ if (!ecc->intr_data)
+ return -ENOMEM;
+
+ ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->edma_unused)
+ return -ENOMEM;
+
+ ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->edma_inuse)
+ return -ENOMEM;
+
ecc->default_queue = info->default_queue;
for (i = 0; i < ecc->num_slots; i++)
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 12/21] dmaengine: edma: Parameter alignment and long line fixes
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (10 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 11/21] dmaengine: edma: Allocate memory dynamically for bitmaps and structures Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 13/21] dmaengine: edma: Use devm_kcalloc when possible Peter Ujfalusi
` (9 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Makes the code a bit more readable.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 84 ++++++++++++++++++++++++++++--------------------------
1 file changed, 44 insertions(+), 40 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 153869c9e13c..bed09ce22ff2 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -294,31 +294,33 @@ static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
val |= or;
edma_write(ecc, offset, val);
}
-static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, int i)
+static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
+ int i)
{
return edma_read(ecc, offset + (i << 2));
}
static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
- unsigned val)
+ unsigned val)
{
edma_write(ecc, offset + (i << 2), val);
}
static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
- unsigned and, unsigned or)
+ unsigned and, unsigned or)
{
edma_modify(ecc, offset + (i << 2), and, or);
}
-static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, unsigned or)
+static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
+ unsigned or)
{
edma_or(ecc, offset + (i << 2), or);
}
static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
- unsigned or)
+ unsigned or)
{
edma_or(ecc, offset + ((i*2 + j) << 2), or);
}
-static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, int j,
- unsigned val)
+static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
+ int j, unsigned val)
{
edma_write(ecc, offset + ((i*2 + j) << 2), val);
}
@@ -326,42 +328,43 @@ static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
{
return edma_read(ecc, EDMA_SHADOW0 + offset);
}
-static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, int offset,
- int i)
+static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
+ int offset, int i)
{
return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
}
-static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, unsigned val)
+static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
+ unsigned val)
{
edma_write(ecc, EDMA_SHADOW0 + offset, val);
}
-static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, int i,
- unsigned val)
+static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
+ int i, unsigned val)
{
edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
}
static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset,
- int param_no)
+ int param_no)
{
return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
}
-static inline void edma_parm_write(struct edma_cc *ecc, int offset, int param_no,
- unsigned val)
+static inline void edma_parm_write(struct edma_cc *ecc, int offset,
+ int param_no, unsigned val)
{
edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
}
-static inline void edma_parm_modify(struct edma_cc *ecc, int offset, int param_no,
- unsigned and, unsigned or)
+static inline void edma_parm_modify(struct edma_cc *ecc, int offset,
+ int param_no, unsigned and, unsigned or)
{
edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
}
static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no,
- unsigned and)
+ unsigned and)
{
edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
}
static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no,
- unsigned or)
+ unsigned or)
{
edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
}
@@ -388,8 +391,8 @@ static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no,
queue_no = ecc->default_queue;
queue_no &= 7;
- edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3),
- ~(0x7 << bit), queue_no << bit);
+ edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit),
+ queue_no << bit);
}
static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
@@ -1134,8 +1137,7 @@ static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
return container_of(c, struct edma_chan, vchan.chan);
}
-static inline struct edma_desc
-*to_edma_desc(struct dma_async_tx_descriptor *tx)
+static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
{
return container_of(tx, struct edma_desc, vdesc.tx);
}
@@ -1256,8 +1258,7 @@ static int edma_terminate_all(struct dma_chan *chan)
edma_stop(echan->ecc, echan->ch_num);
/* Move the cyclic channel back to default queue */
if (echan->edesc->cyclic)
- edma_assign_channel_eventq(echan->ecc,
- echan->ch_num,
+ edma_assign_channel_eventq(echan->ecc, echan->ch_num,
EVENTQ_DEFAULT);
/*
* free the running request descriptor
@@ -1319,9 +1320,10 @@ static int edma_dma_resume(struct dma_chan *chan)
* @direction: Direction of the transfer
*/
static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
- dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
- enum dma_slave_buswidth dev_width, unsigned int dma_length,
- enum dma_transfer_direction direction)
+ dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
+ enum dma_slave_buswidth dev_width,
+ unsigned int dma_length,
+ enum dma_transfer_direction direction)
{
struct edma_chan *echan = to_edma_chan(chan);
struct device *dev = chan->device->dev;
@@ -1467,8 +1469,8 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
return NULL;
}
- edesc = kzalloc(sizeof(*edesc) + sg_len *
- sizeof(edesc->pset[0]), GFP_ATOMIC);
+ edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
+ GFP_ATOMIC);
if (!edesc) {
dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
return NULL;
@@ -1620,8 +1622,8 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
if (nslots > MAX_NR_SG)
return NULL;
- edesc = kzalloc(sizeof(*edesc) + nslots *
- sizeof(edesc->pset[0]), GFP_ATOMIC);
+ edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
+ GFP_ATOMIC);
if (!edesc) {
dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
return NULL;
@@ -1724,13 +1726,17 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
vchan_cyclic_callback(&edesc->vdesc);
goto out;
} else if (edesc->processed == edesc->pset_nr) {
- dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
+ dev_dbg(dev,
+ "Transfer completed on channel %d\n",
+ ch_num);
edesc->residue = 0;
edma_stop(ecc, echan->ch_num);
vchan_cookie_complete(&edesc->vdesc);
echan->edesc = NULL;
} else {
- dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
+ dev_dbg(dev,
+ "Sub transfer completed on channel %d\n",
+ ch_num);
edma_pause(ecc, echan->ch_num);
@@ -1758,14 +1764,14 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
* slot. So we avoid doing so and set the missed flag.
*/
if (p.a_b_cnt == 0 && p.ccnt == 0) {
- dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
+ dev_dbg(dev, "Error on null slot, setting miss\n");
echan->missed = 1;
} else {
/*
* The slot is already programmed but the event got
* missed, so its safe to issue it here.
*/
- dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
+ dev_dbg(dev, "Missed event, TRIGGERING\n");
edma_clean_channel(ecc, echan->ch_num);
edma_stop(ecc, echan->ch_num);
edma_start(ecc, echan->ch_num);
@@ -1870,8 +1876,7 @@ static u32 edma_residue(struct edma_desc *edesc)
* We always read the dst/src position from the first RamPar
* pset. That's the one which is active now.
*/
- pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0],
- dst);
+ pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst);
/*
* Cyclic is simple. Just subtract pset[0].addr from pos.
@@ -1932,8 +1937,7 @@ static enum dma_status edma_tx_status(struct dma_chan *chan,
return ret;
}
-static void __init edma_chan_init(struct edma_cc *ecc,
- struct dma_device *dma,
+static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma,
struct edma_chan *echans)
{
int i, j;
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 13/21] dmaengine: edma: Use devm_kcalloc when possible
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (11 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 12/21] dmaengine: edma: Parameter alignment and long line fixes Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 14/21] dmaengine: edma: Cleanup regarding the use of dev around the code Peter Ujfalusi
` (8 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
When allocating a memory for number of items it is better (looks better)
to use devm_kcalloc.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index bed09ce22ff2..0b46d4263ec6 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -2034,7 +2034,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
* priority. So Q0 is the highest priority queue and the last queue has
* the lowest priority.
*/
- queue_priority_map = devm_kzalloc(dev, (ecc->num_tc + 1) * sizeof(s8),
+ queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
GFP_KERNEL);
if (!queue_priority_map)
return -ENOMEM;
@@ -2065,7 +2065,7 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
u32 shift, offset, mux;
int ret, i;
- xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
+ xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
if (!xbar_chans)
return -ENOMEM;
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 14/21] dmaengine: edma: Cleanup regarding the use of dev around the code
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (12 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 13/21] dmaengine: edma: Use devm_kcalloc when possible Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 15/21] dmaengine: edma: Use dev_dbg instead pr_debug Peter Ujfalusi
` (7 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Be consistent and do not mix the use of dev, &pdev->dev, etc in the
functions.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 0b46d4263ec6..71de1c843bb4 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -1177,7 +1177,7 @@ static void edma_execute(struct edma_chan *echan)
j = i + edesc->processed;
edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
edesc->sg_len += edesc->pset[j].len;
- dev_vdbg(echan->vchan.chan.device->dev,
+ dev_vdbg(dev,
"\n pset[%d]:\n"
" chnum\t%d\n"
" slot\t%d\n"
@@ -1828,7 +1828,6 @@ err_no_chan:
static void edma_free_chan_resources(struct dma_chan *chan)
{
struct edma_chan *echan = to_edma_chan(chan);
- struct device *dev = chan->device->dev;
int i;
/* Terminate transfers */
@@ -1850,7 +1849,7 @@ static void edma_free_chan_resources(struct dma_chan *chan)
echan->alloced = false;
}
- dev_dbg(dev, "freeing channel for %u\n", echan->ch_num);
+ dev_dbg(chan->device->dev, "freeing channel for %u\n", echan->ch_num);
}
/* Send pending descriptor to hardware */
@@ -2174,13 +2173,13 @@ static int edma_probe(struct platform_device *pdev)
return ret;
}
- ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret)
return ret;
- ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
+ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
if (!ecc) {
- dev_err(&pdev->dev, "Can't allocate controller\n");
+ dev_err(dev, "Can't allocate controller\n");
return -ENOMEM;
}
@@ -2325,7 +2324,7 @@ static int edma_probe(struct platform_device *pdev)
ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
- dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
+ dev_err(dev, "Can't allocate PaRAM dummy slot\n");
return ecc->dummy_slot;
}
@@ -2334,7 +2333,7 @@ static int edma_probe(struct platform_device *pdev)
dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask);
- edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
+ edma_dma_init(ecc, &ecc->dma_slave, dev);
edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
@@ -2346,7 +2345,7 @@ static int edma_probe(struct platform_device *pdev)
of_dma_controller_register(node, of_dma_xlate_by_chan_id,
&ecc->dma_slave);
- dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
+ dev_info(dev, "TI EDMA DMA engine driver\n");
return 0;
@@ -2360,8 +2359,8 @@ static int edma_remove(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct edma_cc *ecc = dev_get_drvdata(dev);
- if (pdev->dev.of_node)
- of_dma_controller_free(pdev->dev.of_node);
+ if (dev->of_node)
+ of_dma_controller_free(dev->of_node);
dma_async_device_unregister(&ecc->dma_slave);
edma_free_slot(ecc, ecc->dummy_slot);
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 15/21] dmaengine: edma: Use dev_dbg instead pr_debug
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (13 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 14/21] dmaengine: edma: Cleanup regarding the use of dev around the code Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 16/21] dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toio Peter Ujfalusi
` (6 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
We have access to dev, so it is better to use the dev_dbg for debug prints.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 71de1c843bb4..5b97c11a33af 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -655,14 +655,14 @@ static int edma_start(struct edma_cc *ecc, unsigned channel)
/* EDMA channels without event association */
if (test_bit(channel, ecc->edma_unused)) {
- pr_debug("EDMA: ESR%d %08x\n", j,
- edma_shadow0_read_array(ecc, SH_ESR, j));
+ dev_dbg(ecc->dev, "ESR%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_ESR, j));
edma_shadow0_write_array(ecc, SH_ESR, j, mask);
return 0;
}
/* EDMA channel with event association */
- pr_debug("EDMA: ER%d %08x\n", j,
+ dev_dbg(ecc->dev, "ER%d %08x\n", j,
edma_shadow0_read_array(ecc, SH_ER, j));
/* Clear any pending event or error */
edma_write_array(ecc, EDMA_ECR, j, mask);
@@ -670,8 +670,8 @@ static int edma_start(struct edma_cc *ecc, unsigned channel)
/* Clear any SER */
edma_shadow0_write_array(ecc, SH_SECR, j, mask);
edma_shadow0_write_array(ecc, SH_EESR, j, mask);
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ecc, SH_EER, j));
+ dev_dbg(ecc->dev, "EER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_EER, j));
return 0;
}
@@ -709,8 +709,8 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel)
/* clear possibly pending completion interrupt */
edma_shadow0_write_array(ecc, SH_ICR, j, mask);
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ecc, SH_EER, j));
+ dev_dbg(ecc->dev, "EER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_EER, j));
/* REVISIT: consider guarding against inappropriate event
* chaining by overwriting with dummy_paramset.
@@ -779,8 +779,8 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
- pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
+ dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
+ edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
return 0;
}
@@ -810,8 +810,8 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
int j = (channel >> 5);
unsigned int mask = BIT(channel & 0x1f);
- pr_debug("EDMA: EMR%d %08x\n", j,
- edma_read_array(ecc, EDMA_EMR, j));
+ dev_dbg(ecc->dev, "EMR%d %08x\n", j,
+ edma_read_array(ecc, EDMA_EMR, j));
edma_shadow0_write_array(ecc, SH_ECR, j, mask);
/* Clear the corresponding EMR bits */
edma_write_array(ecc, EDMA_EMCR, j, mask);
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 16/21] dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toio
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (14 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 15/21] dmaengine: edma: Use dev_dbg instead pr_debug Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 17/21] dmaengine: edma: Print warning when linking slots from different eDMA Peter Ujfalusi
` (5 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
edma_write_slot() is for writing an entire paRAM slot.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 5b97c11a33af..e735147ccece 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -949,8 +949,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
edma_setup_interrupt(ecc, channel, NULL, NULL);
/* REVISIT should probably take out of shadow region 0 */
- memcpy_toio(ecc->base + PARM_OFFSET(channel), &dummy_paramset,
- PARM_SIZE);
+ edma_write_slot(ecc, channel, &dummy_paramset);
clear_bit(channel, ecc->edma_inuse);
}
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 17/21] dmaengine: edma: Print warning when linking slots from different eDMA
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (15 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 16/21] dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toio Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 18/21] dmaengine: edma: Consolidate the comments for functions Peter Ujfalusi
` (4 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Warning message in case of linking between paRAM slots in different eDMA
controllers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index e735147ccece..2c6be4c62a73 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -598,6 +598,9 @@ static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
*/
static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
{
+ if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
+ dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
+
from = EDMA_CHAN_SLOT(from);
to = EDMA_CHAN_SLOT(to);
if (from >= ecc->num_slots || to >= ecc->num_slots)
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 18/21] dmaengine: edma: Consolidate the comments for functions
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (16 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 17/21] dmaengine: edma: Print warning when linking slots from different eDMA Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 19/21] dmaengine: edma: Simplify the interrupt handling Peter Ujfalusi
` (3 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
Remove or rewrite the comments for the internal functions.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 86 +++++++-----------------------------------------------
1 file changed, 11 insertions(+), 75 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 2c6be4c62a73..f869d130819b 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -486,19 +486,7 @@ static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch,
}
/*
- * paRAM management functions
- */
-
-/**
- * edma_write_slot - write parameter RAM data for slot
- * @ecc: pointer to edma_cc struct
- * @slot: number of parameter RAM slot being modified
- * @param: data to be written into parameter RAM slot
- *
- * Use this to assign all parameters of a transfer at once. This
- * allows more efficient setup of transfers than issuing multiple
- * calls to set up those parameters in small pieces, and provides
- * complete control over all transfer options.
+ * paRAM slot management functions
*/
static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
const struct edmacc_param *param)
@@ -509,15 +497,6 @@ static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
}
-/**
- * edma_read_slot - read parameter RAM data from slot
- * @ecc: pointer to edma_cc struct
- * @slot: number of parameter RAM slot being copied
- * @param: where to store copy of parameter RAM data
- *
- * Use this to read data from a parameter RAM slot, perhaps to
- * save them as a template for later reuse.
- */
static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
struct edmacc_param *param)
{
@@ -568,15 +547,6 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot)
return EDMA_CTLR_CHAN(ecc->id, slot);
}
-/**
- * edma_free_slot - deallocate DMA parameter RAM
- * @ecc: pointer to edma_cc struct
- * @slot: parameter RAM slot returned from edma_alloc_slot()
- *
- * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
- * Callers are responsible for ensuring the slot is inactive, and will
- * not be activated.
- */
static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
{
@@ -686,10 +656,9 @@ static int edma_start(struct edma_cc *ecc, unsigned channel)
* @ecc: pointer to edma_cc struct
* @channel: channel being deactivated
*
- * When @lch is a channel, any active transfer is paused and
- * all pending hardware events are cleared. The current transfer
- * may not be resumed, and the channel's Parameter RAM should be
- * reinitialized before being reused.
+ * Any active transfer is paused and all pending hardware events are cleared.
+ * The current transfer may not be resumed, and the channel's Parameter RAM
+ * should be reinitialized before being reused.
*/
static void edma_stop(struct edma_cc *ecc, unsigned channel)
{
@@ -721,13 +690,9 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel)
}
}
-/**
- * edma_pause - pause dma on a channel
- * @ecc: pointer to edma_cc struct
- * @channel: on which edma_start() has been called
- *
- * This temporarily disables EDMA hardware events on the specified channel,
- * preventing them from triggering new transfers on its behalf
+/*
+ * Temporarily disable EDMA hardware events on the specified channel,
+ * preventing them from triggering new transfers
*/
static void edma_pause(struct edma_cc *ecc, unsigned channel)
{
@@ -745,13 +710,7 @@ static void edma_pause(struct edma_cc *ecc, unsigned channel)
}
}
-/**
- * edma_resume - resumes dma on a paused channel
- * @ecc: pointer to edma_cc struct
- * @channel: on which edma_pause() has been called
- *
- * This re-enables EDMA hardware events on the specified channel.
- */
+/* Re-enable EDMA hardware events on the specified channel. */
static void edma_resume(struct edma_cc *ecc, unsigned channel)
{
if (ecc->id != EDMA_CTLR(channel)) {
@@ -787,19 +746,6 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
return 0;
}
-/******************************************************************************
- *
- * It cleans ParamEntry qand bring back EDMA to initial state if media has
- * been removed before EDMA has finished.It is usedful for removable media.
- * Arguments:
- * ch_no - channel no
- *
- * Return: zero on success, or corresponding error no on failure
- *
- * FIXME this should not be needed ... edma_stop() should suffice.
- *
- *****************************************************************************/
-
static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
{
if (ecc->id != EDMA_CTLR(channel)) {
@@ -956,14 +902,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
clear_bit(channel, ecc->edma_inuse);
}
-/*
- * edma_assign_channel_eventq - move given channel to desired eventq
- * Arguments:
- * channel - channel number
- * eventq_no - queue to move the channel
- *
- * Can be used to move a channel to a selected event queue.
- */
+/* Move channel to a specific event queue */
static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
enum dma_event_q eventq_no)
{
@@ -986,6 +925,7 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
edma_map_dmach_to_queue(ecc, channel, eventq_no);
}
+/* eDMA interrupt handler */
static irqreturn_t dma_irq_handler(int irq, void *data)
{
struct edma_cc *ecc = data;
@@ -1037,11 +977,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
return IRQ_HANDLED;
}
-/******************************************************************************
- *
- * DMA error interrupt handler
- *
- *****************************************************************************/
+/* eDMA error interrupt handler */
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
struct edma_cc *ecc = data;
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 19/21] dmaengine: edma: Simplify the interrupt handling
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (17 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 18/21] dmaengine: edma: Consolidate the comments for functions Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 20/21] dmaengine: edma: Move the pending error check into helper function Peter Ujfalusi
` (2 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
With the merger of the arch/arm/common/edma.c code into the dmaengine
driver, there is no longer need to have per channel callback/data storage
for interrupt events.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 444 ++++++++++++++++++++++++-----------------------------
1 file changed, 203 insertions(+), 241 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index f869d130819b..5436c811aa2d 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -154,12 +154,6 @@ struct edmacc_param {
#define TCCHEN BIT(22)
#define ITCCHEN BIT(23)
-/*ch_status paramater of callback function possible values*/
-#define EDMA_DMA_COMPLETE 1
-#define EDMA_DMA_CC_ERROR 2
-#define EDMA_DMA_TC1_ERROR 3
-#define EDMA_DMA_TC2_ERROR 4
-
struct edma_pset {
u32 len;
dma_addr_t addr;
@@ -243,12 +237,6 @@ struct edma_cc {
*/
unsigned long *edma_unused;
- struct dma_interrupt_data {
- void (*callback)(unsigned channel, unsigned short ch_status,
- void *data);
- void *data;
- } *intr_data;
-
struct dma_device dma_slave;
struct edma_chan *slave_chans;
int dummy_slot;
@@ -464,24 +452,18 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
return 0;
}
-static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data)
+static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable)
{
lch = EDMA_CHAN_SLOT(lch);
- if (!callback)
- edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
- BIT(lch & 0x1f));
-
- ecc->intr_data[lch].callback = callback;
- ecc->intr_data[lch].data = data;
-
- if (callback) {
+ if (enable) {
edma_shadow0_write_array(ecc, SH_ICR, lch >> 5,
BIT(lch & 0x1f));
edma_shadow0_write_array(ecc, SH_IESR, lch >> 5,
BIT(lch & 0x1f));
+ } else {
+ edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
+ BIT(lch & 0x1f));
}
}
@@ -774,8 +756,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
* edma_alloc_channel - allocate DMA channel and paired parameter RAM
* @ecc: pointer to edma_cc struct
* @channel: specific channel to allocate; negative for "any unmapped channel"
- * @callback: optional; to be issued on DMA completion or errors
- * @data: passed to callback
* @eventq_no: an EVENTQ_* constant, used to choose which Transfer
* Controller (TC) executes requests using this channel. Use
* EVENTQ_DEFAULT unless you really need a high priority queue.
@@ -802,9 +782,7 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
* Returns the number of the channel, else negative errno.
*/
static int edma_alloc_channel(struct edma_cc *ecc, int channel,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data,
- enum dma_event_q eventq_no)
+ enum dma_event_q eventq_no)
{
unsigned done = 0;
int ret = 0;
@@ -860,9 +838,7 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel,
edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));
edma_write_slot(ecc, channel, &dummy_paramset);
- if (callback)
- edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel),
- callback, data);
+ edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true);
edma_map_dmach_to_queue(ecc, channel, eventq_no);
@@ -895,7 +871,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
if (channel >= ecc->num_channels)
return;
- edma_setup_interrupt(ecc, channel, NULL, NULL);
+ edma_setup_interrupt(ecc, channel, false);
/* REVISIT should probably take out of shadow region 0 */
edma_write_slot(ecc, channel, &dummy_paramset);
@@ -925,146 +901,6 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
edma_map_dmach_to_queue(ecc, channel, eventq_no);
}
-/* eDMA interrupt handler */
-static irqreturn_t dma_irq_handler(int irq, void *data)
-{
- struct edma_cc *ecc = data;
- int ctlr;
- u32 sh_ier;
- u32 sh_ipr;
- u32 bank;
-
- ctlr = ecc->id;
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(ecc->dev, "dma_irq_handler\n");
-
- sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
- if (!sh_ipr) {
- sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
- if (!sh_ipr)
- return IRQ_NONE;
- sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
- bank = 1;
- } else {
- sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
- bank = 0;
- }
-
- do {
- u32 slot;
- u32 channel;
-
- dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr);
-
- slot = __ffs(sh_ipr);
- sh_ipr &= ~(BIT(slot));
-
- if (sh_ier & BIT(slot)) {
- channel = (bank << 5) | slot;
- /* Clear the corresponding IPR bits */
- edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
- if (ecc->intr_data[channel].callback)
- ecc->intr_data[channel].callback(
- EDMA_CTLR_CHAN(ctlr, channel),
- EDMA_DMA_COMPLETE,
- ecc->intr_data[channel].data);
- }
- } while (sh_ipr);
-
- edma_shadow0_write(ecc, SH_IEVAL, 1);
- return IRQ_HANDLED;
-}
-
-/* eDMA error interrupt handler */
-static irqreturn_t dma_ccerr_handler(int irq, void *data)
-{
- struct edma_cc *ecc = data;
- int i;
- int ctlr;
- unsigned int cnt = 0;
-
- ctlr = ecc->id;
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(ecc->dev, "dma_ccerr_handler\n");
-
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
- return IRQ_NONE;
-
- while (1) {
- int j = -1;
- if (edma_read_array(ecc, EDMA_EMR, 0))
- j = 0;
- else if (edma_read_array(ecc, EDMA_EMR, 1))
- j = 1;
- if (j >= 0) {
- dev_dbg(ecc->dev, "EMR%d %08x\n", j,
- edma_read_array(ecc, EDMA_EMR, j));
- for (i = 0; i < 32; i++) {
- int k = (j << 5) + i;
- if (edma_read_array(ecc, EDMA_EMR, j) &
- BIT(i)) {
- /* Clear the corresponding EMR bits */
- edma_write_array(ecc, EDMA_EMCR, j,
- BIT(i));
- /* Clear any SER */
- edma_shadow0_write_array(ecc, SH_SECR,
- j, BIT(i));
- if (ecc->intr_data[k].callback) {
- ecc->intr_data[k].callback(
- EDMA_CTLR_CHAN(ctlr, k),
- EDMA_DMA_CC_ERROR,
- ecc->intr_data[k].data);
- }
- }
- }
- } else if (edma_read(ecc, EDMA_QEMR)) {
- dev_dbg(ecc->dev, "QEMR %02x\n",
- edma_read(ecc, EDMA_QEMR));
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ecc, SH_QSECR,
- BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- } else if (edma_read(ecc, EDMA_CCERR)) {
- dev_dbg(ecc->dev, "CCERR %08x\n",
- edma_read(ecc, EDMA_CCERR));
- /* FIXME: CCERR.BIT(16) ignored! much better
- * to just write CCERRCLR with CCERR value...
- */
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_CCERRCLR, BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- }
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
- break;
- cnt++;
- if (cnt > 10)
- break;
- }
- edma_write(ecc, EDMA_EEVAL, 1);
- return IRQ_HANDLED;
-}
-
static inline struct edma_cc *to_edma_cc(struct dma_device *d)
{
return container_of(d, struct edma_cc, dma_slave);
@@ -1646,81 +1482,213 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}
-static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
+static void edma_completion_handler(struct edma_chan *echan)
{
- struct edma_chan *echan = data;
struct edma_cc *ecc = echan->ecc;
struct device *dev = echan->vchan.chan.device->dev;
- struct edma_desc *edesc;
- struct edmacc_param p;
+ struct edma_desc *edesc = echan->edesc;
- edesc = echan->edesc;
+ if (!edesc)
+ return;
spin_lock(&echan->vchan.lock);
- switch (ch_status) {
- case EDMA_DMA_COMPLETE:
- if (edesc) {
- if (edesc->cyclic) {
- vchan_cyclic_callback(&edesc->vdesc);
- goto out;
- } else if (edesc->processed == edesc->pset_nr) {
- dev_dbg(dev,
- "Transfer completed on channel %d\n",
- ch_num);
- edesc->residue = 0;
- edma_stop(ecc, echan->ch_num);
- vchan_cookie_complete(&edesc->vdesc);
- echan->edesc = NULL;
- } else {
- dev_dbg(dev,
- "Sub transfer completed on channel %d\n",
- ch_num);
-
- edma_pause(ecc, echan->ch_num);
-
- /* Update statistics for tx_status */
- edesc->residue -= edesc->sg_len;
- edesc->residue_stat = edesc->residue;
- edesc->processed_stat = edesc->processed;
- }
- edma_execute(echan);
+ if (edesc->cyclic) {
+ vchan_cyclic_callback(&edesc->vdesc);
+ spin_unlock(&echan->vchan.lock);
+ return;
+ } else if (edesc->processed == edesc->pset_nr) {
+ dev_dbg(dev, "Transfer completed on channel %d\n",
+ echan->ch_num);
+ edesc->residue = 0;
+ edma_stop(ecc, echan->ch_num);
+ vchan_cookie_complete(&edesc->vdesc);
+ echan->edesc = NULL;
+ } else {
+ dev_dbg(dev, "Sub transfer completed on channel %d\n",
+ echan->ch_num);
+
+ edma_pause(ecc, echan->ch_num);
+
+ /* Update statistics for tx_status */
+ edesc->residue -= edesc->sg_len;
+ edesc->residue_stat = edesc->residue;
+ edesc->processed_stat = edesc->processed;
+ }
+ edma_execute(echan);
+
+ spin_unlock(&echan->vchan.lock);
+}
+
+/* eDMA interrupt handler */
+static irqreturn_t dma_irq_handler(int irq, void *data)
+{
+ struct edma_cc *ecc = data;
+ int ctlr;
+ u32 sh_ier;
+ u32 sh_ipr;
+ u32 bank;
+
+ ctlr = ecc->id;
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(ecc->dev, "dma_irq_handler\n");
+
+ sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
+ if (!sh_ipr) {
+ sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
+ if (!sh_ipr)
+ return IRQ_NONE;
+ sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
+ bank = 1;
+ } else {
+ sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
+ bank = 0;
+ }
+
+ do {
+ u32 slot;
+ u32 channel;
+
+ dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr);
+
+ slot = __ffs(sh_ipr);
+ sh_ipr &= ~(BIT(slot));
+
+ if (sh_ier & BIT(slot)) {
+ channel = (bank << 5) | slot;
+ /* Clear the corresponding IPR bits */
+ edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
+ edma_completion_handler(&ecc->slave_chans[channel]);
}
- break;
- case EDMA_DMA_CC_ERROR:
- edma_read_slot(ecc, echan->slot[0], &p);
+ } while (sh_ipr);
+
+ edma_shadow0_write(ecc, SH_IEVAL, 1);
+ return IRQ_HANDLED;
+}
+
+static void edma_error_handler(struct edma_chan *echan)
+{
+ struct edma_cc *ecc = echan->ecc;
+ struct device *dev = echan->vchan.chan.device->dev;
+ struct edmacc_param p;
+
+ if (!echan->edesc)
+ return;
+
+ spin_lock(&echan->vchan.lock);
+ edma_read_slot(ecc, echan->slot[0], &p);
+ /*
+ * Issue later based on missed flag which will be sure
+ * to happen as:
+ * (1) we finished transmitting an intermediate slot and
+ * edma_execute is coming up.
+ * (2) or we finished current transfer and issue will
+ * call edma_execute.
+ *
+ * Important note: issuing can be dangerous here and
+ * lead to some nasty recursion when we are in a NULL
+ * slot. So we avoid doing so and set the missed flag.
+ */
+ if (p.a_b_cnt == 0 && p.ccnt == 0) {
+ dev_dbg(dev, "Error on null slot, setting miss\n");
+ echan->missed = 1;
+ } else {
/*
- * Issue later based on missed flag which will be sure
- * to happen as:
- * (1) we finished transmitting an intermediate slot and
- * edma_execute is coming up.
- * (2) or we finished current transfer and issue will
- * call edma_execute.
- *
- * Important note: issuing can be dangerous here and
- * lead to some nasty recursion when we are in a NULL
- * slot. So we avoid doing so and set the missed flag.
+ * The slot is already programmed but the event got
+ * missed, so its safe to issue it here.
*/
- if (p.a_b_cnt == 0 && p.ccnt == 0) {
- dev_dbg(dev, "Error on null slot, setting miss\n");
- echan->missed = 1;
- } else {
- /*
- * The slot is already programmed but the event got
- * missed, so its safe to issue it here.
+ dev_dbg(dev, "Missed event, TRIGGERING\n");
+ edma_clean_channel(ecc, echan->ch_num);
+ edma_stop(ecc, echan->ch_num);
+ edma_start(ecc, echan->ch_num);
+ edma_trigger_channel(ecc, echan->ch_num);
+ }
+ spin_unlock(&echan->vchan.lock);
+}
+
+/* eDMA error interrupt handler */
+static irqreturn_t dma_ccerr_handler(int irq, void *data)
+{
+ struct edma_cc *ecc = data;
+ int i;
+ int ctlr;
+ unsigned int cnt = 0;
+
+ ctlr = ecc->id;
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(ecc->dev, "dma_ccerr_handler\n");
+
+ if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
+ (edma_read(ecc, EDMA_QEMR) == 0) &&
+ (edma_read(ecc, EDMA_CCERR) == 0))
+ return IRQ_NONE;
+
+ while (1) {
+ int j = -1;
+ if (edma_read_array(ecc, EDMA_EMR, 0))
+ j = 0;
+ else if (edma_read_array(ecc, EDMA_EMR, 1))
+ j = 1;
+ if (j >= 0) {
+ dev_dbg(ecc->dev, "EMR%d %08x\n", j,
+ edma_read_array(ecc, EDMA_EMR, j));
+ for (i = 0; i < 32; i++) {
+ int k = (j << 5) + i;
+ if (edma_read_array(ecc, EDMA_EMR, j) &
+ BIT(i)) {
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ecc, EDMA_EMCR, j,
+ BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR,
+ j, BIT(i));
+ edma_error_handler(&ecc->slave_chans[k]);
+ }
+ }
+ } else if (edma_read(ecc, EDMA_QEMR)) {
+ dev_dbg(ecc->dev, "QEMR %02x\n",
+ edma_read(ecc, EDMA_QEMR));
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ecc, EDMA_QEMCR, BIT(i));
+ edma_shadow0_write(ecc, SH_QSECR,
+ BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ } else if (edma_read(ecc, EDMA_CCERR)) {
+ dev_dbg(ecc->dev, "CCERR %08x\n",
+ edma_read(ecc, EDMA_CCERR));
+ /* FIXME: CCERR.BIT(16) ignored! much better
+ * to just write CCERRCLR with CCERR value...
*/
- dev_dbg(dev, "Missed event, TRIGGERING\n");
- edma_clean_channel(ecc, echan->ch_num);
- edma_stop(ecc, echan->ch_num);
- edma_start(ecc, echan->ch_num);
- edma_trigger_channel(ecc, echan->ch_num);
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ecc, EDMA_CCERRCLR, BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
}
- break;
- default:
- break;
+ if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
+ (edma_read(ecc, EDMA_QEMR) == 0) &&
+ (edma_read(ecc, EDMA_CCERR) == 0))
+ break;
+ cnt++;
+ if (cnt > 10)
+ break;
}
-out:
- spin_unlock(&echan->vchan.lock);
+ edma_write(ecc, EDMA_EEVAL, 1);
+ return IRQ_HANDLED;
}
/* Alloc channel resources */
@@ -1732,8 +1700,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
int a_ch_num;
LIST_HEAD(descs);
- a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num,
- edma_callback, echan, EVENTQ_DEFAULT);
+ a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT);
if (a_ch_num < 0) {
ret = -ENODEV;
@@ -2154,11 +2121,6 @@ static int edma_probe(struct platform_device *pdev)
if (!ecc->slave_chans)
return -ENOMEM;
- ecc->intr_data = devm_kcalloc(dev, ecc->num_channels,
- sizeof(*ecc->intr_data), GFP_KERNEL);
- if (!ecc->intr_data)
- return -ENOMEM;
-
ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
sizeof(unsigned long), GFP_KERNEL);
if (!ecc->edma_unused)
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 20/21] dmaengine: edma: Move the pending error check into helper function
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (18 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 19/21] dmaengine: edma: Simplify the interrupt handling Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:37 ` [PATCH 21/21] dmaengine: edma: Simplify and optimize ccerr interrupt handler Peter Ujfalusi
2015-09-10 8:47 ` [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Arnd Bergmann
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
In the ccerr interrupt handler the code checks for pending errors in the
error status registers in two different places.
Move the check out to a helper function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 5436c811aa2d..f1e898525ae6 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -1608,6 +1608,16 @@ static void edma_error_handler(struct edma_chan *echan)
spin_unlock(&echan->vchan.lock);
}
+static inline bool edma_error_pending(struct edma_cc *ecc)
+{
+ if (edma_read_array(ecc, EDMA_EMR, 0) ||
+ edma_read_array(ecc, EDMA_EMR, 1) ||
+ edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
+ return true;
+
+ return false;
+}
+
/* eDMA error interrupt handler */
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
@@ -1622,10 +1632,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
dev_dbg(ecc->dev, "dma_ccerr_handler\n");
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
+ if (!edma_error_pending(ecc))
return IRQ_NONE;
while (1) {
@@ -1678,10 +1685,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
}
}
}
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
+ if (!edma_error_pending(ecc))
break;
cnt++;
if (cnt > 10)
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 21/21] dmaengine: edma: Simplify and optimize ccerr interrupt handler
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (19 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 20/21] dmaengine: edma: Move the pending error check into helper function Peter Ujfalusi
@ 2015-09-10 8:37 ` Peter Ujfalusi
2015-09-10 8:47 ` [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Arnd Bergmann
21 siblings, 0 replies; 27+ messages in thread
From: Peter Ujfalusi @ 2015-09-10 8:37 UTC (permalink / raw)
To: vinod.koul, nsekhar, linux
Cc: olof, arnd, linux-arm-kernel, linux-kernel, linux-omap, dmaengine
No need to run through the bits in QEMR and CCERR events since they will
not trigger any action, so just clearing the errors there is fine.
In case of the missed event the loop can be optimized so we spend less time
to handle the event.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 64 ++++++++++++++++++++----------------------------------
1 file changed, 23 insertions(+), 41 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index f1e898525ae6..81302daf687c 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -1625,6 +1625,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
int i;
int ctlr;
unsigned int cnt = 0;
+ unsigned int val;
ctlr = ecc->id;
if (ctlr < 0)
@@ -1637,54 +1638,35 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
while (1) {
int j = -1;
- if (edma_read_array(ecc, EDMA_EMR, 0))
+ if ((val = edma_read_array(ecc, EDMA_EMR, 0)))
j = 0;
- else if (edma_read_array(ecc, EDMA_EMR, 1))
+ else if ((val = edma_read_array(ecc, EDMA_EMR, 1)))
j = 1;
if (j >= 0) {
- dev_dbg(ecc->dev, "EMR%d %08x\n", j,
- edma_read_array(ecc, EDMA_EMR, j));
- for (i = 0; i < 32; i++) {
+ unsigned long emr = val;
+
+ dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
+ for (i = find_next_bit(&emr, 32, 0); i < 32;
+ i = find_next_bit(&emr, 32, i + 1)) {
int k = (j << 5) + i;
- if (edma_read_array(ecc, EDMA_EMR, j) &
- BIT(i)) {
- /* Clear the corresponding EMR bits */
- edma_write_array(ecc, EDMA_EMCR, j,
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR, j,
BIT(i));
- /* Clear any SER */
- edma_shadow0_write_array(ecc, SH_SECR,
- j, BIT(i));
- edma_error_handler(&ecc->slave_chans[k]);
- }
- }
- } else if (edma_read(ecc, EDMA_QEMR)) {
- dev_dbg(ecc->dev, "QEMR %02x\n",
- edma_read(ecc, EDMA_QEMR));
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ecc, SH_QSECR,
- BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- } else if (edma_read(ecc, EDMA_CCERR)) {
- dev_dbg(ecc->dev, "CCERR %08x\n",
- edma_read(ecc, EDMA_CCERR));
- /* FIXME: CCERR.BIT(16) ignored! much better
- * to just write CCERRCLR with CCERR value...
- */
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_CCERRCLR, BIT(i));
-
- /* NOTE: not reported!! */
- }
+ edma_error_handler(&ecc->slave_chans[k]);
}
+ } else if ((val = edma_read(ecc, EDMA_QEMR))) {
+ dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
+ /* Not reported, just clear the interrupt reason. */
+ edma_write(ecc, EDMA_QEMCR, val);
+ edma_shadow0_write(ecc, SH_QSECR, val);
+ } else if ((val = edma_read(ecc, EDMA_CCERR))) {
+ dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
+ /* Not reported, just clear the interrupt reason. */
+ edma_write(ecc, EDMA_CCERRCLR, val);
}
+
if (!edma_error_pending(ecc))
break;
cnt++;
--
2.5.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one
2015-09-10 8:37 [PATCH 00/21] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi
` (20 preceding siblings ...)
2015-09-10 8:37 ` [PATCH 21/21] dmaengine: edma: Simplify and optimize ccerr interrupt handler Peter Ujfalusi
@ 2015-09-10 8:47 ` Arnd Bergmann
21 siblings, 0 replies; 27+ messages in thread
From: Arnd Bergmann @ 2015-09-10 8:47 UTC (permalink / raw)
To: Peter Ujfalusi
Cc: vinod.koul, nsekhar, linux, olof, linux-arm-kernel, linux-kernel,
linux-omap, dmaengine
On Thursday 10 September 2015 11:37:29 Peter Ujfalusi wrote:
>
> with this series the edma two driver setup will be changed to have only one
> driver to support eDMA3. The legacy edma interface will be removed and eDMA can
> only be used via dmaengine API from this point on.
> In order to do the merge the following improvements has been done:
> - One driver instance per eDMA:
> - Any number of eDMA instances are supported (both legacy and DT boot)
> - Not relying on global variables, arrays, etc
> - Code simplification and optimizations in several places
>
> This change will also help us to do bigger changes in the eDMA driver since,
> since now we have only one driver to work with.
>
Very nice series, thanks for addressing this long-standing issue!
I've briefly read over the series and did not see anything major
sticking out, but I did not attempt to do a thorough review.
I found two minor things that I commented on that could be improved.
Arnd
^ permalink raw reply [flat|nested] 27+ messages in thread