From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752565AbbIPCac (ORCPT ); Tue, 15 Sep 2015 22:30:32 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:46089 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752308AbbIPCa3 (ORCPT ); Tue, 15 Sep 2015 22:30:29 -0400 MIME-version: 1.0 Content-type: text/plain; charset=windows-1252 X-AuditID: cbfee691-f79ca6d00000456a-9f-55f8d443f576 Content-transfer-encoding: 8BIT Message-id: <55F8D442.5020004@samsung.com> Date: Wed, 16 Sep 2015 11:30:26 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 To: =?windows-1252?Q?Heiko_St=FCbner?= Cc: ulf.hansson@linaro.org, mturquette@baylibre.com, sboyd@codeaurora.org, linux-mmc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru M Stan , CPGS Subject: Re: [PATCH 6/8] mmc: dw_mmc: Generic MMC tuning with the clock phase framework References: <1441045446-30858-1-git-send-email-heiko@sntech.de> <1441045446-30858-7-git-send-email-heiko@sntech.de> <55F7D602.70003@samsung.com> <8878355.D5Q8mk4qcM@diego> In-reply-to: <8878355.D5Q8mk4qcM@diego> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsWyRsSkSNf5yo9Qg1PTlSwaXkxitXh5SNPi /6PXrBabHl9jtfjYc4/V4vKuOWwWR/73M1p8evCf2eLiKVeLH2e6WSyOrw134PZ4f6OV3WN2 w0UWj8t9vUwed67tYfPYvKTeo2/LKkaP7dfmMXt83iQXwBHFZZOSmpNZllqkb5fAlTFvRWXB E6GKSVcnszUw/uXrYuTkkBAwkTi7+D8bhC0mceHeejBbSGAFo0Tv1lKYmusPWoHiXEDxpYwS Cz9eASviFRCU+DH5HksXIwcHs4C8xJFL2RCmnsT9i1oQ5Q8YJc4cmMAEUa4l0TJlDTOIzSKg KjFh50qwMWwCOhLbvx0HqxEVCJM4M6ODBcQWEbCQmH5pBzPIIGaBDUwSN3s7mUEWCAtESuxa FAixYD2jxL5jEA2cAuoSSxb3sIAkJAT+sktc+nqXBWKbgMS3yYfADpUQkJXYdIAZ4jFJiYMr brBMYBSbheSdWQjvzEJ4ZwEj8ypG0dSC5ILipPQiU73ixNzi0rx0veT83E2MwGg9/e/ZxB2M 9w9YH2IU4GBU4uGNaP8eKsSaWFZcmXuI0RTohonMUqLJ+cCUkFcSb2hsZmRhamJqbGRuaaYk zqsj/TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA2N4jNa7NJ/rv0WUH8QyuqQpr4n3Zar+ uvv0vWetJhdK5tjtC766ysWGveVZNfNztRcLBLaqF2b0Tr6xeJHllHQntyabHVxbjItfvF22 PW3b3v37njXd7kzr97fVEJp9h5FX3X6Oo80rRQn2+hcnNkUoGjYkTq4xTD9c2ejbO0l61o5s F9bddkosxRmJhlrMRcWJAOLqc0TRAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphleLIzCtJLcpLzFFi42I5/e+xgK7zlR+hBjOfS1s0vJjEavHykKbF /0evWS02Pb7GavGx5x6rxeVdc9gsjvzvZ7T49OA/s8XFU64WP850s1gcXxvuwO3x/kYru8fs hossHpf7epk87lzbw+axeUm9R9+WVYwe26/NY/b4vEkugCOqgdEmIzUxJbVIITUvOT8lMy/d Vsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB+hMJYWyxJxSoFBAYnGxkr4dpgmhIW66 FjCNEbq+IUFwPUYGaCBhDWPGvBWVBU+EKiZdnczWwPiXr4uRk0NCwETi+oNWNghbTOLCvfVA NheHkMBSRomFH6+AJXgFBCV+TL7H0sXIwcEsIC9x5FI2hKkncf+iFkT5A0aJMwcmMEGUa0m0 TFnDDGKzCKhKTNi5EmwMm4COxPZvx8FqRAXCJM7M6GABsUUELCSmX9rBDDKIWWADk8TN3k5m kAXCApESuxYFQixYzyix7xhEA6eAusSSxT0sExgFZiE5bxbCebMQzlvAyLyKUSK1ILmgOCk9 1zAvtVyvODG3uDQvXS85P3cTIzglPJPawXhwl/shRgEORiUe3oj276FCrIllxZW5hxglOJiV RHh79/8IFeJNSaysSi3Kjy8qzUktPsRoCvTfRGYp0eR8YLrKK4k3NDYxM7I0Mje0MDI2VxLn lV35LFRIID2xJDU7NbUgtQimj4mDU6qBUazz5MmU01yJ5o1ZC37VOE9SWLk1YumyaRO3sXlY fWvg63ilnF8qZKh0X66Cp9HxSRTPbt2NE2fJdWpOCGCSuLipliP93q5ktxZF8eVNN/a7PdBY a2f0sFJF5dvH2Ef/NnpfSbSbJcV4R7o/aq/P29dBJv9WhvqyzFgQ+1venqt7n9XSzlwHJZbi jERDLeai4kQAuxnIpB8DAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 09/16/2015 07:09 AM, Heiko Stübner wrote: > Hi, > > Am Dienstag, 15. September 2015, 17:25:38 schrieb Jaehoon Chung: >> On 09/01/2015 03:24 AM, Heiko Stuebner wrote: >>> From: Alexandru M Stan >>> >>> This algorithm will try 1 degree increments, since there's no way to tell >>> what resolution the underlying phase code uses. As an added bonus, doing >>> many tunings yields better results since some tests are run more than once >>> (ex: if the underlying driver uses 45 degree increments, the tuning code >>> will try the same angle more than once). >>> >>> It will then construct a list of good phase ranges (even ranges that cross >>> 360/0), will pick the biggest range then it will set the sample_clk to the >>> middle of that range. >>> >>> We do not touch ciu_drive (and by extension define default-drive-phase). >>> Drive phase is mostly used to define minimum hold times, while one could >>> write some code to determine what phase meets the minimum hold time (ex 10 >>> degrees) this will not work with the current clock phase framework (which >>> floors angles, so we'll get 0 deg, and there's no way to know what >>> resolution the floors happen at). We assume that the default drive angles >>> set by the hardware are good enough. >>> >>> If a device has device specific code (like exynos) then that will still >>> take precedence, otherwise this new code will execute. If the device wants >>> to tune, but has no sample_clk defined we'll return EIO with an error >>> message. >> >> Which point is "_generic_"? I don't find the code that control the register >> relevant to CLK_DRV/SMPL PHASE. It seems that posted the similar patches at >> u-boot mailing list.. > > The "generic" part is that it uses the clk phase API for dw_mmc > implementations where the clkgen controlling interface is outside the dw_mmc > IP itself. So it's open for other implementations as well. Designware IP also has the CLK phase register(UHS_REG_EXT register)... if this code is related with it, it should be located into dw-mmc.c. > > But if you are more comfortable with it, I can also move it into the dw_mmc- > rockchip variant for the time being, until another user comes along. I think more better that this code is located into dw_mmc-rockchip. how about? Best Regards, Jaehoon Chung > > > Heiko > >