From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752980AbbIQCD6 (ORCPT ); Wed, 16 Sep 2015 22:03:58 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:48961 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752377AbbIQCDz (ORCPT ); Wed, 16 Sep 2015 22:03:55 -0400 MIME-version: 1.0 Content-type: text/plain; charset=windows-1252 X-AuditID: cbfee68e-f79c56d000006efb-5c-55fa1f89d766 Content-transfer-encoding: 8BIT Message-id: <55FA1F88.3090108@samsung.com> Date: Thu, 17 Sep 2015 11:03:52 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 To: =?windows-1252?Q?Heiko_St=FCbner?= Cc: ulf.hansson@linaro.org, mturquette@baylibre.com, sboyd@codeaurora.org, linux-mmc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru M Stan , CPGS Subject: Re: [PATCH 6/8] mmc: dw_mmc: Generic MMC tuning with the clock phase framework References: <1441045446-30858-1-git-send-email-heiko@sntech.de> <8878355.D5Q8mk4qcM@diego> <55F8D442.5020004@samsung.com> <2272810.k4vHSW5D0y@diego> In-reply-to: <2272810.k4vHSW5D0y@diego> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsWyRsSkWLdT/leoQfdNYYuGF5NYLV4e0rT4 /+g1q8Wmx9dYLT723GO1uLxrDpvFkf/9jBafHvxntrh4ytXix5luFovja8MduD3e32hl95jd cJHF43JfL5PHnWt72Dw2L6n36NuyitFj+7V5zB6fN8kFcERx2aSk5mSWpRbp2yVwZWxa9ZCt YJ5UxYmlZ9gbGDtEuxg5OSQETCSW/1jJDmGLSVy4t56ti5GLQ0hgBaPE+0tHWGCKmvftZIFI zGKUmP/nJViCV0BQ4sfke0A2BwezgLzEkUvZEKaexP2LWhDlDxgl1v55CFWuJTF9XiMTiM0i oCpx+N4nZhCbTUBHYvu342BxUYEwiTMzOsDqRQQsJKZf2sEMMohZYAOTxM3eTmaQBcICkRK7 FgWC1AgJzGCUOHzMAMTmFFCXmHL9GxNIvYRAI4fE+gkLWCGWCUh8m3wI7E4JAVmJTQeYIf6S lDi44gbLBEaxWUi+mYXwzSyEbxYwMq9iFE0tSC4oTkovMtIrTswtLs1L10vOz93ECIzX0/+e 9e1gvHnA+hCjAAejEg/vi2c/QoVYE8uKK3MPMZoC3TCRWUo0OR+YFPJK4g2NzYwsTE1MjY3M Lc2UxHkTpH4GCwmkJ5akZqemFqQWxReV5qQWH2Jk4uCUamBUVJ7xO71NeUK4S0pbzvPzMfdD f6g/mfw18KfCsaDDbqbVBbOfLX794PzVF3r75PXu6+mr+GfN+dM6MXvH5ycrbG/adMUpeWvn hX6NZ+lveMRgXR6seD3It26hjZLcqQuHJl9ealy0fmOXvlgAU+6PQ1vmVR5j0ODImbCm8LWU 0vycvll7ZzxXYinOSDTUYi4qTgQATWULYtICAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphleLIzCtJLcpLzFFi42I5/e+xoG6n/K9Qg+PreC0aXkxitXh5SNPi /6PXrBabHl9jtfjYc4/V4vKuOWwWR/73M1p8evCf2eLiKVeLH2e6WSyOrw134PZ4f6OV3WN2 w0UWj8t9vUwed67tYfPYvKTeo2/LKkaP7dfmMXt83iQXwBHVwGiTkZqYklqkkJqXnJ+SmZdu q+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SmkkJZYk4pUCggsbhYSd8O04TQEDdd C5jGCF3fkCC4HiMDNJCwhjFj06qHbAXzpCpOLD3D3sDYIdrFyMkhIWAi0bxvJwuELSZx4d56 ti5GLg4hgVmMEvP/vARL8AoISvyYfA/I5uBgFpCXOHIpG8LUk7h/UQui/AGjxNo/D6HKtSSm z2tkArFZBFQlDt/7xAxiswnoSGz/dhwsLioQJnFmRgdYvYiAhcT0SzuYQQYxC2xgkrjZ28kM skBYIFJi16JAkBohgRmMEoePGYDYnALqElOuf2OawAh0JMJ1sxCum4Vw3QJG5lWMEqkFyQXF Sem5hnmp5XrFibnFpXnpesn5uZsYwSnhmdQOxoO73A8xCnAwKvHwvnj2I1SINbGsuDL3EKME B7OSCO9MgV+hQrwpiZVVqUX58UWlOanFhxhNgd6byCwlmpwPTFd5JfGGxiZmRpZG5oYWRsbm SuK8siufhQoJpCeWpGanphakFsH0MXFwSjUw6pw5s3eC1Xm21bXlV97n/ikVC/c5scBdnnWZ 2KtkT+Hpnqfy425GzPy814H/htHu8JA7x0Pfp7kfEGNMijjoq/YjjzOz8APnOkOVoGt9rXp7 tbtO76vuvceTfviMpsHlJz+ENXUvc9/P23h/b4zd1nYNI+eAFyJJmWuSctov/D+2I5bh/Mdu JZbijERDLeai4kQAXm1lFB8DAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 09/16/2015 11:52 PM, Heiko Stübner wrote: > Hi, > > Am Mittwoch, 16. September 2015, 11:30:26 schrieb Jaehoon Chung: >> On 09/16/2015 07:09 AM, Heiko Stübner wrote: >>> Am Dienstag, 15. September 2015, 17:25:38 schrieb Jaehoon Chung: >>>> On 09/01/2015 03:24 AM, Heiko Stuebner wrote: >>>>> From: Alexandru M Stan >>>>> >>>>> This algorithm will try 1 degree increments, since there's no way to >>>>> tell >>>>> what resolution the underlying phase code uses. As an added bonus, doing >>>>> many tunings yields better results since some tests are run more than >>>>> once >>>>> (ex: if the underlying driver uses 45 degree increments, the tuning code >>>>> will try the same angle more than once). >>>>> >>>>> It will then construct a list of good phase ranges (even ranges that >>>>> cross >>>>> 360/0), will pick the biggest range then it will set the sample_clk to >>>>> the >>>>> middle of that range. >>>>> >>>>> We do not touch ciu_drive (and by extension define default-drive-phase). >>>>> Drive phase is mostly used to define minimum hold times, while one could >>>>> write some code to determine what phase meets the minimum hold time (ex >>>>> 10 >>>>> degrees) this will not work with the current clock phase framework >>>>> (which >>>>> floors angles, so we'll get 0 deg, and there's no way to know what >>>>> resolution the floors happen at). We assume that the default drive >>>>> angles >>>>> set by the hardware are good enough. >>>>> >>>>> If a device has device specific code (like exynos) then that will still >>>>> take precedence, otherwise this new code will execute. If the device >>>>> wants >>>>> to tune, but has no sample_clk defined we'll return EIO with an error >>>>> message. >>>> >>>> Which point is "_generic_"? I don't find the code that control the >>>> register >>>> relevant to CLK_DRV/SMPL PHASE. It seems that posted the similar patches >>>> at >>>> u-boot mailing list.. >>> >>> The "generic" part is that it uses the clk phase API for dw_mmc >>> implementations where the clkgen controlling interface is outside the >>> dw_mmc IP itself. So it's open for other implementations as well. >> >> Designware IP also has the CLK phase register(UHS_REG_EXT register)... >> if this code is related with it, it should be located into dw-mmc.c. > > UHS_REG_EXT is acutally "reserved" on both the rk3288 as well as the rk3368. > rk3036/rk3128 (Cortex-A7) provide a bit description, but the tuning > documentation still uses the controls located in the clock controller. > > So I guess UHS_REG_EXT is the real "generic" solution. > >>> But if you are more comfortable with it, I can also move it into the >>> dw_mmc- rockchip variant for the time being, until another user comes >>> along. >> I think more better that this code is located into dw_mmc-rockchip. how >> about? > > As described above, moving that to the rockchip part sounds sensible. And I > guess we can think more about it, once a second user appears. Sure, we can think more about this. As you knew, clock phase is closely related to the timing issue. So clock phase scheme needs to control however. In future, if somebody introduce the similar control as rockchip, we can discuss about it. Best Regards, Jaehoon Chung > > > Heiko >