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Fri, 21 Aug 2026 09:35:43 -0700 (PDT) X-Received: by 2002:a17:90b:5303:b0:38e:5ac1:9517 with SMTP id 98e67ed59e1d1-395c354cbffmr14302327a91.3.1787330143403; Fri, 21 Aug 2026 09:35:43 -0700 (PDT) Received: from [192.168.1.2] ([122.171.20.211]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395c4c194d2sm3737725a91.15.2026.08.21.09.35.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Aug 2026 09:35:43 -0700 (PDT) Message-ID: <55d15218-d812-4b4f-a3a8-ebe02ee26f2b@oss.qualcomm.com> Date: Fri, 21 Aug 2026 22:05:34 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 10/15] dt-bindings: clock: qcom: Add Kuno Global Clock Controller To: Krzysztof Kozlowski Cc: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Taniya Das , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org References: <20260809-kuno-soc-support-v1-0-5e0ede4a0c72@oss.qualcomm.com> <20260809-kuno-soc-support-v1-10-5e0ede4a0c72@oss.qualcomm.com> <20260813-glorious-secret-mantis-dcc083@quoll> Content-Language: en-US From: Hardeep Sharma In-Reply-To: <20260813-glorious-secret-mantis-dcc083@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDEzMCBTYWx0ZWRfX2NLCej04HSxu K5mUaJXdVH92dznqno2CBPn1cgMojnuMQi0xLOxe7z+xqjm5+MgtcDFIGmST1oM78tM0k7yk22k fZ+XI8sFOtvIuJyqCpxtlrMn//Ln6nbsveYU9ugIgmHkWUOJprr5oyIsHrtcIVR/8ovt7q4XwVX raWdWfRGAN/xUZxaq3bJd8e2pgouyn19KjKOI71I8t5UlhsCpE8ZcwLkDQH2c0T/XWIx1jsmW77 gZIOIkdAu3oTGNvnkIvJNMHDS+n1BLF+ACGMfNIyr/u5b1GJr75teyN1RZRQCoNcgqb9DgEPsqa Lc668c0AjsynqWqvED8Htpp8+FuBQASulkJ4Fwu6n/nHa3MmXsyII9yZZO2DLB+gM2d/i8k7dDY gcIV8BN6dyvK0VZp/xhKRdAvKI41v2M5xY3PZ1SfrbMWAviLsMGeLd6YHu0mnS+bRU6WO8TjzBA qKrnYbnqJabEw608TkQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDEzMCBTYWx0ZWRfX6uxyR/62oCq1 ag0JthV5hQPQl8ss30NJ1Ftjv50rlN49FCjnTelF6Lc/QQDuMPIaHoT51Uo2qQlPC9yCDr0f7Wx D6pH/gMgYUKPobYTo+kXXo0b3kW4qOA= X-Authority-Analysis: v=2.4 cv=DdQnbPtW c=1 sm=1 tr=0 ts=6a887e60 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=+KmVXPE0btiop/5qwQKk0Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=gEfo2CItAAAA:8 a=tqvfEU5OP8eIFZPyU8cA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: OdDTcLSG4pO7tipVUM1-OCkSUPGIQXyB X-Proofpoint-GUID: OdDTcLSG4pO7tipVUM1-OCkSUPGIQXyB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_05,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210130 On 8/13/2026 3:10 PM, Krzysztof Kozlowski wrote: > On Sun, Aug 09, 2026 at 12:57:09PM +0530, Hardeep Sharma wrote: >> Add the device tree binding and clock/reset IDs for the global clock >> controller (GCC) on the Qualcomm Kuno SoC so its device trees can >> describe the GCC block and reference the clocks and resets it provides. > Almost each of your bindings commit has different style. I would assume > this you would write once and copy-paste. Thanks for review. Corrected in v3 : https://lore.kernel.org/all/20260821-kuno-soc-support-v3-0-196e2b306368@oss.qualcomm.com/ Best Wishes Hardeep Sharma >> Signed-off-by: Hardeep Sharma >> --- >> .../devicetree/bindings/clock/qcom,kuno-gcc.yaml | 56 +++++++++++++ >> include/dt-bindings/clock/qcom,kuno-gcc.h | 95 ++++++++++++++++++++++ >> 2 files changed, 151 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml >> new file mode 100644 >> index 000000000000..ff01ff31c2e2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml >> @@ -0,0 +1,56 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,kuno-gcc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Global Clock & Reset Controller on Kuno >> + >> +maintainers: >> + - Hardeep Sharma >> + >> +description: | >> + Qualcomm global clock control module provides the clocks and resets on Kuno. >> + >> + See also: include/dt-bindings/clock/qcom,kuno-gcc.h >> + >> +properties: >> + compatible: >> + const: qcom,kuno-gcc >> + >> + clocks: >> + items: >> + - description: Board XO source >> + - description: Board active-only XO source >> + - description: Sleep clock source >> + - description: PCIe pipe clock source >> + >> + power-domains: >> + items: >> + - description: CX domain >> + >> +required: >> + - compatible >> + - clocks > Not a power domain provider? Then it should not be allowed or explain > oddities in the commit msg. Thanks for review. Apologies. The GCC does host GDSCs, so it genuinely is a power-domain provider. Rather than disallowing #power-domain-cells, in v3 I've made it "required" in qcom,kuno-gcc.yaml and declared #power-domain-cells = <1> on the SoC gcc node, following qcom,sdx75-gcc. v3: https://lore.kernel.org/all/20260821-kuno-soc-support-v3-0-196e2b306368@oss.qualcomm.com/ Best Wishes Hardeep Sharma > >> + >> +allOf: >> + - $ref: qcom,gcc.yaml# >> + >> +unevaluatedProperties: false > Best regards, > Krzysztof >