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Subject: Re: [PATCH 0/6] Implement generic IPI support mechanism
To: Thomas Gleixner <tglx@linutronix.de>
References: <1443019758-20620-1-git-send-email-qais.yousef@imgtec.com>
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CC: Jiang Liu <jiang.liu@linux.intel.com>, <linux-kernel@vger.kernel.org>,
        <marc.zyngier@arm.com>, <jason@lakedaemon.net>,
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From: Qais Yousef <qais.yousef@imgtec.com>
Message-ID: <560BECDE.7090405@imgtec.com>
Date: Wed, 30 Sep 2015 15:08:30 +0100
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On 09/30/2015 03:03 PM, Thomas Gleixner wrote:
> On Wed, 30 Sep 2015, Qais Yousef wrote:
>
>> On 09/29/2015 09:48 PM, Thomas Gleixner wrote:
>>> 	 Now how these hwirqs are allocated is a domain/architecture
>>> 	 specific issue.
>>>
>>> 	 x86 will just find a vector which is available on all target
>>> 	 cpus and mark it as used. That's a single hw irq number.
>>>
>>> 	 mips and others, which implement IPIs as regular hw interrupt
>>> 	 numbers, will allocate a these (consecutive) hw interrupt
>>> 	 numbers either from a reserved region or just from the
>>> 	 regular space. That's a bunch of hw irq numbers and we need
>>> 	 to come up with a proper storage format in the irqdata for
>>> 	 that. That might be
>>>
>>> 	       struct ipi_mapping {
>>> 		      unsigned int	nr_hwirqs;
>>> 		      unsigned int	cpumap[NR_CPUS];
>>> 	       };
>> Can we use NR_CPUS here? If we run in UP configuration for instance, this will
>> be one. The coprocessor could be outside the NR_CPUS range in general, no?
>>
>> How about
>>
>>                          struct ipi_mapping {
>>                                  unsigned int        nr_hwirqs;
>>                                  unsigned int        nr_cpus;
>>                                  unsigned int        *cpumap;
>>                          }
>>
>> where cpumap is dynamically allocated by the controller which has better
>> knowledge about the supported cpu range it can talk to?
> Sure. As I said: 'That might be' ....
>   
>


OK thanks. I just wanted to make sure I didn't misunderstand anything.

Will try to send an updated version with all the changes soon.

Thanks,
Qais