From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755930AbbJAF6J (ORCPT ); Thu, 1 Oct 2015 01:58:09 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:33442 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755167AbbJAF6E (ORCPT ); Thu, 1 Oct 2015 01:58:04 -0400 Subject: Re: [PATCH 01/11 RESEND] ARM: OMAP: DRA7: hwmod: Add data for McASP3 To: Tero Kristo , Paul Walmsley References: <1442326206-30192-1-git-send-email-peter.ujfalusi@ti.com> <560BB434.6080308@ti.com> <560BDCF8.20909@ti.com> CC: , , , From: Peter Ujfalusi Message-ID: <560CCB54.60306@ti.com> Date: Thu, 1 Oct 2015 08:57:40 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <560BDCF8.20909@ti.com> Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/30/2015 04:00 PM, Tero Kristo wrote: >>>> +/* l4_per2 -> mcasp3 */ >>>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { >>>> + .master = &dra7xx_l4_per2_hwmod, >>>> + .slave = &dra7xx_mcasp3_hwmod, >>> >>> So this is the low-speed control/register access port, where the MPU >>> writes to the McASP3 config registers... >>> >>>> + .clk = "l3_iclk_div", >>> >>> ... and thus this interface clock doesn't look right for this port, since >>> it's most likely generated from the L4PER2, where this port is connected. >>> So it should probably be "l4_iclk_div". >> >> There is no "l4_iclk_div" for dra7xx. Looking around the file all other script >> generated data uses "l3_iclk_div" for IPs under dra7xx_l4_per2_hwmod. >> >> Tero: do you know the reason for this? > > This comes from the autogen generated data. Looking at the hwdb data for dra7, > it seems l3 clock is defined as the OCP input clock for most of the modules. > > Looking at TRM, we also have L3 ICK defined as the interface clock for GPIO > modules for example, and also mcasp modules. > > I think this is just a documentation issue and we are missing a divide by 2 > from all interface clocks, the interface clocks are coming from l4 > interconnects and the interconnect chapter still clearly states that the l4 > clock is l3 clock / 2. It seams that we have the clock node for the l4_iclk_div, but it is called as l4_root_clk_div. I will use this in the mcasp3 hwmod patch. -- Péter