From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751887AbbJLKve (ORCPT ); Mon, 12 Oct 2015 06:51:34 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:53376 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751346AbbJLKvc (ORCPT ); Mon, 12 Oct 2015 06:51:32 -0400 X-AuditID: cbfee691-f79d66d000001509-fb-561b90b15b40 Message-id: <561B90B1.1090100@samsung.com> Date: Mon, 12 Oct 2015 19:51:29 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-version: 1.0 To: Anand Moon , Krzysztof Kozlowski Cc: Kukjin Kim , Javier Martinez Canillas , Lukasz Majewski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "linux-samsung-soc@vger.kernel.org" , Linux Kernel Subject: Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support References: <1444578364-1384-1-git-send-email-linux.amoon@gmail.com> <1444578364-1384-3-git-send-email-linux.amoon@gmail.com> <561B48B7.1040201@samsung.com> In-reply-to: Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrLIsWRmVeSWpSXmKPExsWyRsSkSHfjBOkwg9c7zSzmHznHavHm7Rom i9cvDC36H79mtnjzcDOjxabH11gtLu+aw2Yx4/w+Jot1G2+xO3B67Jx1l91j06pONo/NS+o9 tvQDeX1bVjF6fN4kF8AWxWWTkpqTWZZapG+XwJWx59g89oKF0hXdLf0sDYz7RLsYOTkkBEwk Dr1/zwZhi0lcuLceyObiEBJYwSgx/fledpiih//esYLYQgKzgBJfEiDsB4wSL+dHg9i8AloS 35/vAatnEVCVeHDjCiOIzSagI7H923EmEFtUIEziwbq9rBD1ghI/Jt9jAbFFBMIlpny/zwKy mFngAJPE7SUvga7g4BAWiJA4cdUI4qDnjBL911cyg8Q5BYIl9iwVATGZBdQlpkzJBRnDLCAv sXnNW2aQcgmBl+wSu683Qt0jIPFt8iEWkHoJAVmJTQeYId6SlDi44gbLBEaxWUgumoUwdRaS qQsYmVcxiqYWJBcUJ6UXmeoVJ+YWl+al6yXn525iBMbi6X/PJu5gvH/A+hCjAAejEg8vxxap MCHWxLLiytxDjKZAR0xklhJNzgdGfF5JvKGxmZGFqYmpsZG5pZmSOK+O9M9gIYH0xJLU7NTU gtSi+KLSnNTiQ4xMHJxSDYwHm69OW203I9PFl0ViU1Hc/BePX01qSXh0I+A7W171rB7+FRFP TI7pnF+9eorc7etcqwTYlwiZx917KMcULPm60e/el6iTE49mZOxfsK7c7uUOpd2NM0yu/M2q LAv0rnM+f3SSoOlBJZPX02/e/a6X/HVXTWKSGod9YG9c5u44IzOF1jzZZYeVWIozEg21mIuK EwHb1N8PwAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFIsWRmVeSWpSXmKPExsVy+t9jQd2NE6TDDG49NrCYf+Qcq8Wbt2uY LF6/MLTof/ya2eLNw82MFpseX2O1uLxrDpvFjPP7mCzWbbzF7sDpsXPWXXaPTas62Tw2L6n3 2NIP5PVtWcXo8XmTXABbVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5i bqqtkotPgK5bZg7QUUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjD3H 5rEXLJSu6G7pZ2lg3CfaxcjJISFgIvHw3ztWCFtM4sK99WwgtpDALEaJ6V8SIOwHjBIv50eD 2LwCWhLfn+9hB7FZBFQlHty4wghiswnoSGz/dpwJxBYVCJN4sG4vK0S9oMSPyfdYQGwRgXCJ Kd/vA9lcHMwCB5gkbi95CbSMg0NYIELixFUjkLiQwHNGif7rK5lB4pwCwRJ7loqAmMwC6hJT puSCjGEWkJfYvOYt8wRGoBsRNsxCqJqFpGoBI/MqRonUguSC4qT0XKO81HK94sTc4tK8dL3k /NxNjOB4fya9g/HwLvdDjAIcjEo8vBxbpMKEWBPLiitzDzFKcDArifC6tkuHCfGmJFZWpRbl xxeV5qQWH2I0BQbBRGYp0eR8YCrKK4k3NDYxM7I0Mje0MDI2VxLnvXGIIUxIID2xJDU7NbUg tQimj4mDU6qBUfmkhhp3mu17/4aWqYuzrh8+4/0wZ9mzfRvb1T61cbBcXiG1STvscTyrw0em hxG9bA+z/ZjS4ib9V92p3prn/i6c7+RSuSOFnmt2fN5zuZXF/0Kr5dK3FQeN7KWUBD44Vpqm SXwU4jSydMrdJnjPff1F68nJqwTOm7eurnv44Xbmvpb82SbpSizFGYmGWsxFxYkAVnfeFQ0D AAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/12/2015 07:46 PM, Anand Moon wrote: > Hi Krzysztof, > > On 12 October 2015 at 11:14, Krzysztof Kozlowski > wrote: >> On 12.10.2015 00:46, Anand Moon wrote: >>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >> >> This description is not entirely correct. The MMC driver already >> supports these UHS speeds (you did not any code) so you rather enabled >> it (description of bindings says "is supported"). >> >> You mentioned DDR50 but I don't see respective property below. > Looks like I missed it, I will add this in the next patch, >> >> How do you know that these modes are really supported? I don't know. Can >> you convince me? >> > >>> >>> Signed-off-by: Anand Moon >>> >>> --- >>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>> >>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >> >> I don't get what is exactly fixed here. What was the error? What is the >> outcome of this fix? The log below is before or after? >> >> Best regards, >> Krzysztof >> >>> >>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>> [ 2.461743] mmcblk0: p1 p2 >> >>> --- >>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> index 58c06d3..ba4a87b 100644 >>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> @@ -364,6 +364,10 @@ >>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>> bus-width = <4>; >>> cap-sd-highspeed; >>> + sd-uhs-sdr12; >>> + sd-uhs-sdr25; >>> + sd-uhs-sdr50; >>> + sd-uhs-sdr104; >>> }; >>> >>> &pinctrl_0 { >>> >> > > Changes were made to support Sandisk Ultra UHS-I class 10 card support. > OdroidXU3/XU4 board would not boot up using this card. > > Depending on the capability of the UHS-I card, the speed of the card > is selected. > I have just added the enhance capability feature to support them. > > On warm boot: i.e reboot of the board. > [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot > req 50000000Hz, actual 50000000HZ div = 0) > [ 4.657555] mmc1: new high speed SDHC card at address aaaa > [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 4.669206] mmcblk0: p1 p2 > > On cold boot:: ie: power on the board. > > [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot > req 100000000Hz, actual 100000000HZ div = 0) > [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa > [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB > [ 4.650293] IRQ56 no longer affine to CPU7 > [ 4.650581] CPU7: shutdown > [ 4.658293] mmcblk0: p1 p2 > > Note: Their is need to reset the PMIC > S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers > to support this feature consistently on every reboot. I don't understand...why needs to reset? I know it needs to switch the voltage, doesn't it? Best Regards, Jaehoon Chung > > -Anand Moon >