From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751900AbbJLVqv (ORCPT ); Mon, 12 Oct 2015 17:46:51 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:38897 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751601AbbJLVqs (ORCPT ); Mon, 12 Oct 2015 17:46:48 -0400 Subject: Re: [PATCH v2 1/4] ARM: dts: dra7: Add dt node for the sycon pcie To: Tony Lindgren References: <1442323985-29939-1-git-send-email-kishon@ti.com> <1442323985-29939-2-git-send-email-kishon@ti.com> <20151012212149.GZ23801@atomide.com> CC: , , , , , , , , , , , From: Kishon Vijay Abraham I Message-ID: <561C2A1B.3000201@ti.com> Date: Tue, 13 Oct 2015 03:16:03 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <20151012212149.GZ23801@atomide.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Tony, On Tuesday 13 October 2015 02:51 AM, Tony Lindgren wrote: > * Kishon Vijay Abraham I [150915 06:37]: >> Add new device tree node for the control module register space where >> PCIe registers are present. >> >> Signed-off-by: Kishon Vijay Abraham I >> --- >> arch/arm/boot/dts/dra7.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi >> index 5d65db9..0769b5d 100644 >> --- a/arch/arm/boot/dts/dra7.dtsi >> +++ b/arch/arm/boot/dts/dra7.dtsi >> @@ -154,6 +154,11 @@ >> compatible = "syscon"; >> reg = <0x1c04 0x0020>; >> }; >> + >> + scm_conf_pcie: tisyscon@1c24 { >> + compatible = "syscon"; >> + reg = <0x1c24 0x0024>; >> + }; >> }; >> >> cm_core_aon: cm_core_aon@5000 { > > > Why don't you just extend the existing scm_conf1 area? This is not all pcie > specific for scm_conf_pcie, at least for PLLEN_CONTROL, RMII_CLK_SETTING > and MUXSEL_32K_CLKIN. scm_conf_pcie has only PCIe registers (it starts at 0x4A003C24). PLLEN_CONTROL and others are at 0x4A003C14 as per DRA75x_DRA74x_SR1.1_NDA_TRM_vW. Since PCIe itself has a bunch of registers for itself, thought of creating a separate dt node. But I can extend scm_conf1 area. Thanks Kishon