From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752579AbbJNI7y (ORCPT ); Wed, 14 Oct 2015 04:59:54 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:41018 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751478AbbJNI7t (ORCPT ); Wed, 14 Oct 2015 04:59:49 -0400 Message-ID: <561E1957.5030503@hisilicon.com> Date: Wed, 14 Oct 2015 16:59:03 +0800 From: Zhou Wang User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 To: Arnd Bergmann CC: Gabriele Paoloni , Bjorn Helgaas , Bjorn Helgaas , "jingoohan1@gmail.com" , "pratyush.anand@gmail.com" , "linux@arm.linux.org.uk" , "thomas.petazzoni@free-electrons.com" , "lorenzo.pieralisi@arm.com" , "james.morse@arm.com" , "Liviu.Dudau@arm.com" , "jason@lakedaemon.net" , "robh@kernel.org" , "gabriel.fernandez@linaro.org" , "Minghuan.Lian@freescale.com" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , zhangjukuo , qiuzhenfa , "liudongdong (C)" , qiujiang , "xuwei (O)" , "Liguozhu (Kenneth)" , "Wangkefeng (Kevin)" , Rob Herring Subject: Re: [PATCH v10 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 References: <1444445957-239522-1-git-send-email-wangzhou1@hisilicon.com> <6336414.HvfCQcuT3Y@wuerfel> <11677087.JbqAo0FWJE@wuerfel> In-Reply-To: <11677087.JbqAo0FWJE@wuerfel> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.66.65.131] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.561E1978.008D,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 18dac23c1b1f8c213f80a9f44578ed88 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015/10/13 23:00, Arnd Bergmann wrote: > On Tuesday 13 October 2015 14:49:07 Gabriele Paoloni wrote: >>> On Monday 12 October 2015 16:35:45 Bjorn Helgaas wrote: >>>> >>>>> +{ >>>>> + u64 addr; >>>>> + struct device_node *msi_node; >>>>> + struct resource res; >>>>> + struct device_node *np = pp->dev->of_node; >>>>> + struct hisi_pcie *pcie = to_hisi_pcie(pp); >>>>> + >>>>> + msi_node = of_parse_phandle(np, "msi-parent", 0); >>>>> + if (!msi_node) { >>>>> + dev_err(pp->dev, "failed to find msi-parent\n"); >>>>> + return -EINVAL; >>>>> + } >>>>> + of_address_to_resource(msi_node, 0, &res); >>>> >>>> Does this use the "msi-parent" node in the same way as other drivers >>>> do? I'm sure there must be other places where we extract struct >>>> resource information from an "msi-parent" node, but I don't see them. >>>> >>>> I'm trying to verify that this isn't some kind of incompatible >>>> extension of the "msi-parent" property. I cc'd Arnd and Rob (DT >>>> experts). >>> >>> This is not ok, what this does is that it relies on a particular >>> implementation of the MSI controller and directly accesses its >>> registers. >> >> Hi Arnd, thanks for reviewing. >> >> What we do is to retrieve the msi-parent physical address and we store it >> in our internal PCIe register locations... > > Ah, thanks for the clarification, I missed that part. > >> So we do not operate directly on the msi controller registers... >> >> So I wonder if the current implementation is Ok to retrieve the >> msi-parent address.... > > Not sure. Why do you do this? Normally the PCI host does not know > or care about the address of the MSI controller, because the messages > are just passed up to the parent bus as DMA transfers. > Hi Arnd, In Hip05 PCIe host, it uses GITS_TRANSLATER's address to get TLP package which contains MSI address and MSI data, and then combine BDF and MSI data to a 32 bit data which will be writen to GITS_TRANSLATER register of ITS. I think maybe this is a defect of our PCIe controller. > I don't think what you do here is safe because the 'reg' property > of the MSI controller might point to the address that is used for > the message directly. I see your point, however we must get address of GITS_TRANSLATER and set it to PCIe host. How about adding necessary comments here? Best Regards, Zhou > > Arnd > > . >