From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753924AbbJNNea (ORCPT ); Wed, 14 Oct 2015 09:34:30 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:10350 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753471AbbJNNe2 (ORCPT ); Wed, 14 Oct 2015 09:34:28 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 14 Oct 2015 06:26:16 -0700 Subject: Re: [PATCH V2 2/2] dmaengine: tegra-adma: Add support for Tegra210 ADMA To: Vinod Koul References: <1444047007-30494-1-git-send-email-jonathanh@nvidia.com> <1444047007-30494-3-git-send-email-jonathanh@nvidia.com> <20151014112759.GS27370@localhost> CC: Laxman Dewangan , Stephen Warren , Thierry Reding , "Alexandre Courbot" , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Arnd Bergmann" , , , From: Jon Hunter Message-ID: <561E59DC.6040608@nvidia.com> Date: Wed, 14 Oct 2015 14:34:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20151014112759.GS27370@localhost> X-Originating-IP: [10.21.132.152] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/10/15 12:27, Vinod Koul wrote: > On Mon, Oct 05, 2015 at 01:10:07PM +0100, Jon Hunter wrote: > >> +static enum dma_status tegra_adma_tx_status(struct dma_chan *dc, >> + dma_cookie_t cookie, >> + struct dma_tx_state *txstate) >> +{ >> + struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); >> + struct tegra_adma_desc *desc; >> + struct virt_dma_desc *vd; >> + enum dma_status ret; >> + unsigned long flags; >> + unsigned int residual; >> + >> + spin_lock_irqsave(&tdc->lock, flags); >> + >> + ret = dma_cookie_status(dc, cookie, txstate); >> + if (ret == DMA_COMPLETE) { >> + spin_unlock_irqrestore(&tdc->lock, flags); >> + return ret; >> + } > > txstate can be NULL, upon which below code doesn't help in getting executed > so bailing here or above case is fine Ok, will fix. >> +static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic( >> + struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, >> + size_t period_len, enum dma_transfer_direction direction, >> + unsigned long flags) >> +{ >> + struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); >> + struct tegra_adma_desc *desc = NULL; >> + >> + if (!tdc->config_valid) { >> + dev_err(tdc2dev(tdc), "ADMA slave configuration not set\n"); >> + return NULL; >> + } >> + >> + if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) { >> + dev_err(tdc2dev(tdc), "invalid buffer/period len\n"); >> + return NULL; >> + } >> + >> + if (buf_len % period_len) { >> + dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n"); >> + return NULL; >> + } >> + >> + if (!IS_ALIGNED(buf_addr, 4)) { >> + dev_err(tdc2dev(tdc), "invalid buffer alignment\n"); >> + return NULL; >> + } >> + >> + desc = kzalloc(sizeof(*desc), GFP_ATOMIC); > > we recommend GFP_NOWAIT for the subsystem Ok, makes sense. I should probably fix up the tegra APB dma driver too. >> +static int tegra_adma_remove(struct platform_device *pdev) >> +{ >> + struct tegra_adma *tdma = platform_get_drvdata(pdev); >> + struct tegra_adma_chan *tdc; >> + int i; >> + >> + dma_async_device_unregister(&tdma->dma_dev); >> + >> + for (i = 0; i < tdma->nr_channels; ++i) { >> + tdc = &tdma->channels[i]; >> + tasklet_kill(&tdc->vc.task); >> + } > this is good, but your irq is still active and can fire and thus trigger > more tasklets! Ah, yes. Will fix. Thanks! Jon