From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753077AbbJONvq (ORCPT ); Thu, 15 Oct 2015 09:51:46 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:53270 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751048AbbJONvo (ORCPT ); Thu, 15 Oct 2015 09:51:44 -0400 Message-ID: <561FAF51.4090101@huawei.com> Date: Thu, 15 Oct 2015 21:51:13 +0800 From: Jian Zhou User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 To: Paolo Bonzini , , , , , , , , , CC: , Subject: Re: [PATCH] KVM: VMX: enable LBR virtualization References: <1444471906-8496-1-git-send-email-jianjay.zhou@huawei.com> <561BA323.7090002@huawei.com> <561BAB15.8090700@redhat.com> <561E3BDB.4080904@huawei.com> <561E3CC8.7080309@redhat.com> In-Reply-To: <561E3CC8.7080309@redhat.com> Content-Type: text/plain; charset="gbk"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.177.19.14] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.561FAF6A.0048,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a7ade47b431b46113a0e7e26bcd56a6d Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015/10/14 19:30, Paolo Bonzini wrote: > > > On 14/10/2015 13:26, Jian Zhou wrote: >> On 12/10/2015 20:44, Paolo Bonzini wrote: >>> In addition, the MSR numbers may differ between the guest and the host, >>> because it is possible to emulate e.g. a Core CPU on a Core 2 CPU. So I >>> recommend against using the atomic switch mechanism for the from/to MSRs. >> >> The vLBR feature depends on vPMU, and to enable vPMU, it needs to >> specify the "cpu mode" in the guest XML as host-passthrough. I think >> the MSR numbers between the guest and the host are the same in this >> senario. > > Does it depend on vPMU _for Linux guests_ or in general? My impression > is that LBR can be used by the guest independent of the PMU. I think only for Linux guests. I googled how to enable LBR on other guests(except Linux guests), e.g. Windows, and got no developer manuals about it. Here is an article about it: http://www.codeproject.com/Articles/517466/Last-branch-records- and-branch-tracing it says: "bit 8 of DR7 represents bit 0 of DebugCtl. This is the LBR bit." Intel developer manual vol 3B introduced DR7(Debug Control Register) and bit 8 of it on Section 17.2.4: "LE and GE (local and global exact breakpoint enable) flags (bits 8, 9) ¡ª When set, these flags cause the processor to detect the exact instruction that caused a data breakpoint condition. For backward and forward compatibility with other Intel processors, we recommend that the LE and GE flags be set to 1 if exact breakpoints are required." But for now, I don't know how to test bit 8 of DR7 on Windows. Regards, Jian > > >