From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753424AbbJOPDP (ORCPT ); Thu, 15 Oct 2015 11:03:15 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59677 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752289AbbJOPDN (ORCPT ); Thu, 15 Oct 2015 11:03:13 -0400 Subject: Re: [PATCH] KVM: VMX: enable LBR virtualization To: Jian Zhou , herongguang.he@huawei.com, zhang.zhanghailiang@huawei.com, gleb@kernel.org, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <1444471906-8496-1-git-send-email-jianjay.zhou@huawei.com> <561BA323.7090002@huawei.com> <561BAB15.8090700@redhat.com> <561E3BDB.4080904@huawei.com> <561E3CC8.7080309@redhat.com> <561FAF51.4090101@huawei.com> Cc: weidong.huang@huawei.com, peter.huangpeng@huawei.com From: Paolo Bonzini Message-ID: <561FC028.8000006@redhat.com> Date: Thu, 15 Oct 2015 17:03:04 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <561FAF51.4090101@huawei.com> Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15/10/2015 15:51, Jian Zhou wrote: > > > On 2015/10/14 19:30, Paolo Bonzini wrote: >> >> >> On 14/10/2015 13:26, Jian Zhou wrote: >>> On 12/10/2015 20:44, Paolo Bonzini wrote: >>>> In addition, the MSR numbers may differ between the guest and the host, >>>> because it is possible to emulate e.g. a Core CPU on a Core 2 CPU. >>>> So I >>>> recommend against using the atomic switch mechanism for the from/to >>>> MSRs. >>> >>> The vLBR feature depends on vPMU, and to enable vPMU, it needs to >>> specify the "cpu mode" in the guest XML as host-passthrough. I think >>> the MSR numbers between the guest and the host are the same in this >>> senario. >> >> Does it depend on vPMU _for Linux guests_ or in general? My impression >> is that LBR can be used by the guest independent of the PMU. > > I think only for Linux guests. > > I googled how to enable LBR on other guests(except Linux guests), > e.g. Windows, and got no developer manuals about it. > > Here is an article about it: > http://www.codeproject.com/Articles/517466/Last-branch-records- > and-branch-tracing > it says: > "bit 8 of DR7 represents bit 0 of DebugCtl. This is the LBR bit." Don't worry about the operating system in the guest: you are just emulating a processor feature, you do not care about anything except what is written in the Intel SDM. You can use kvm-unit-tests (https://git.kernel.org/cgit/virt/kvm/kvm-unit-tests.git/) to write a test for your feature. There are existing tests for debugging features. Thanks, Paolo