From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753497AbbJPITX (ORCPT ); Fri, 16 Oct 2015 04:19:23 -0400 Received: from bhuna.collabora.co.uk ([93.93.135.160]:44102 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751514AbbJPITP (ORCPT ); Fri, 16 Oct 2015 04:19:15 -0400 Subject: Re: [PATCH v2 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain To: Krzysztof Kozlowski , linux-kernel@vger.kernel.org References: <1444905084-22540-1-git-send-email-tomeu.vizoso@collabora.com> <1444905084-22540-3-git-send-email-tomeu.vizoso@collabora.com> <56203A74.7040305@samsung.com> Cc: Gustavo Padovan , Javier Martinez Canillas , Seung-Woo Kim , Kukjin Kim , Inki Dae , Kyungmin Park , Joonyoung Shim , Russell King , devicetree@vger.kernel.org, Kumar Gala , Ian Campbell , linux-samsung-soc@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , linux-arm-kernel@lists.infradead.org From: Tomeu Vizoso Message-ID: <5620B2FC.5040004@collabora.com> Date: Fri, 16 Oct 2015 10:19:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <56203A74.7040305@samsung.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/16/2015 01:44 AM, Krzysztof Kozlowski wrote: > On 15.10.2015 19:31, Tomeu Vizoso wrote: >> Adds to the node of the DISP1 power domain the two clocks that need to >> be reparented while the domain is powered off: >> CLK_MOUT_ACLK200_DISP1_SUB and CLK_MOUT_ACLK300_DISP1_SUB. >> >> Otherwise the state is unknown at power up and the mixer's clocks are >> all messed up. >> >> Signed-off-by: Tomeu Vizoso >> Link: http://lkml.kernel.org/g/561CDC33.7050103@collabora.com >> --- >> >> >> arch/arm/boot/dts/exynos5250.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi >> index b24610ea8c2a..88b9cf5f226f 100644 >> --- a/arch/arm/boot/dts/exynos5250.dtsi >> +++ b/arch/arm/boot/dts/exynos5250.dtsi >> @@ -130,6 +130,10 @@ >> compatible = "samsung,exynos4210-pd"; >> reg = <0x100440A0 0x20>; >> #power-domain-cells = <0>; >> + clocks = <&clock CLK_FIN_PLL>, >> + <&clock CLK_MOUT_ACLK200_DISP1_SUB>, >> + <&clock CLK_MOUT_ACLK300_DISP1_SUB>; >> + clock-names = "oscclk", "clk0", "clk1"; >> }; >> >> clock: clock-controller@10010000 { >> > > I reviewed it already. Any changes here since v1? No, I just forgot to add your r-b tag, sorry about that. Thanks, Tomeu