From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752607AbbJQAuL (ORCPT ); Fri, 16 Oct 2015 20:50:11 -0400 Received: from regular2.263xmail.com ([211.157.152.3]:57879 "EHLO regular2.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751644AbbJQAuI (ORCPT ); Fri, 16 Oct 2015 20:50:08 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: amstan@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: <82416a1c5419fd34510544ca38e8acf6> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 01/10] clk: rockchip: Add sclk_mipidsi_24m for mipi dsi To: Stephen Boyd References: <1444470930-17150-1-git-send-email-zyw@rock-chips.com> <1444470930-17150-2-git-send-email-zyw@rock-chips.com> <20151016213940.GA10182@codeaurora.org> Cc: heiko@sntech.de, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Michael Turquette , Jeff Chen , linux-kernel@vger.kernel.org, Doug Anderson , Kumar Gala , "David S. Miller" , Ian Campbell , Sonny Rao , Rob Herring , linux-arm-kernel@lists.infradead.org, Pawel Moll , Mark Rutland , Huang Lin , Roger Chen , Alexandru M Stan From: Chris Zhong Message-ID: <56219B2C.8090902@rock-chips.com> Date: Sat, 17 Oct 2015 08:49:48 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20151016213940.GA10182@codeaurora.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/17/2015 05:39 AM, Stephen Boyd wrote: > On 10/10, Chris Zhong wrote: >> sclk_mipidsi_24m is the gating of mipi dsi phy. >> >> Signed-off-by: Chris Zhong >> --- > Acked-by: Stephen Boyd > >> drivers/clk/rockchip/clk-rk3288.c | 2 +- >> include/dt-bindings/clock/rk3288-cru.h | 1 + >> 2 files changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c >> index 9040878..c7d7ebf 100644 >> --- a/drivers/clk/rockchip/clk-rk3288.c >> +++ b/drivers/clk/rockchip/clk-rk3288.c >> @@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { >> GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), >> GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), >> GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), >> - GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), >> + GATE(SCLK_MIPI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), >> > It would have been better to make #defines for all these clocks > even if they weren't going to be used here. Then we could have > applied this patch directly to clk tree without having a clk tree > to arm-soc dependency. > Thanks for your great suggestion, I'll defines all clocks at next version patch serial