From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754032AbbJSRU5 (ORCPT ); Mon, 19 Oct 2015 13:20:57 -0400 Received: from g2t4622.austin.hp.com ([15.73.212.79]:35850 "EHLO g2t4622.austin.hp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753849AbbJSRU4 (ORCPT ); Mon, 19 Oct 2015 13:20:56 -0400 Message-ID: <56252676.8020308@hpe.com> Date: Mon, 19 Oct 2015 13:20:54 -0400 From: Waiman Long User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130109 Thunderbird/10.0.12 MIME-Version: 1.0 To: Peter Zijlstra CC: ling.ma.program@gmail.com, mingo@redhat.com, linux-kernel@vger.kernel.org, Ma Ling Subject: Re: [RFC PATCH] qspinlock: Improve performance by reducing load instruction rollback References: <1445221642-15319-1-git-send-email-ling.ma.program@gmail.com> <20151019093304.GI3816@twins.programming.kicks-ass.net> In-Reply-To: <20151019093304.GI3816@twins.programming.kicks-ass.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/19/2015 05:33 AM, Peter Zijlstra wrote: > On Mon, Oct 19, 2015 at 10:27:22AM +0800, ling.ma.program@gmail.com wrote: >> From: Ma Ling >> >> All load instructions can run speculatively but they have to follow >> memory order rule in multiple cores as below: >> _x = _y = 0 >> >> Processor 0 Processor 1 >> >> mov r1, [ _y] //M1 mov [ _x], 1 //M3 >> mov r2, [ _x] //M2 mov [ _y], 1 //M4 >> >> If r1 = 1, r2 must be 1 >> >> In order to guarantee above rule, although Processor 0 execute >> M1 and M2 instruction out of order, they are kept in ROB, >> when load buffer for _x in Processor 0 received the update >> message from Processor 1, Processor 0 need to roll back >> from M2 instruction, which will flush the whole pipeline, >> the latency is over the penalty from branch prediction miss. >> >> In this patch we use lock cmpxchg instruction to force load >> instructions to be serialization, the destination operand >> receives a write cycle without regard to the result of >> the comparison, which can help us to reduce the penalty >> from load instruction roll back. >> >> Our experiment indicates the performance can be improved by 10%~15% >> for 2 and 3 threads cases, the conflicts from lock cache line >> spend them most of the time. > On what hardware? Also, you forgot to Cc Waiman, who is a prime author > of this code. Excessive quoting for his benefit. Thanks for letting me aware of this patch. I had commented on the patch in a separate mail. Cheers, Longman