From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752235AbbJTL2n (ORCPT ); Tue, 20 Oct 2015 07:28:43 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16003 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751050AbbJTL2m (ORCPT ); Tue, 20 Oct 2015 07:28:42 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 20 Oct 2015 04:27:13 -0700 Subject: Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options To: Stephen Warren , Thierry Reding References: <1444987441-25176-1-git-send-email-jonathanh@nvidia.com> <56212308.7050405@wwwdotorg.org> CC: Linus Walleij , Alexandre Courbot , , , From: Jon Hunter Message-ID: <56262563.3020201@nvidia.com> Date: Tue, 20 Oct 2015 12:28:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <56212308.7050405@wwwdotorg.org> X-Originating-IP: [10.21.132.159] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/10/15 17:17, Stephen Warren wrote: > On 10/16/2015 03:24 AM, Jon Hunter wrote: >> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the >> Tegra124 >> documentation implies that all functions (pcie, usb3 and sata) can be >> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has >> been confirmed that this is not the case and the mux'ing options much >> more >> limited. Unfortunately, the public documentation has not been updated to >> reflect this and so detail the actual mux'ing options here by function: > > FWIW, there's better documentation of this in the Tegra210 TRM, although > the options have been expanded on that chip, so the docs don't entirely > apply to Tegra124. > >> Function: Lanes: >> pcie1 x2: pcie3, pcie4 >> pcie1 x4: pcie1, pcie2, pcie3, pcie4 >> pcie2 x1 (option1): pcie0 >> pcie2 x1 (option2): pcie2 >> usb3 port 0: pcie0 >> usb3 port 1 (option 1): pcie1 >> usb3 port 1 (option 2): sata0 >> sata: sata0 > > I think this change needs a DT binding change to go along with it. Can > you take a look at: > > http://www.spinics.net/lists/arm-kernel/msg449647.html > [PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210 I took a look at the above and it looks fine to me. Do you want me to put the above info into the DT binding doc? I am not sure that we need to update the binding itself. Jon