From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932207AbbJUKBJ (ORCPT ); Wed, 21 Oct 2015 06:01:09 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:54926 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751092AbbJUKBG (ORCPT ); Wed, 21 Oct 2015 06:01:06 -0400 Subject: Re: [PATCH] EDAC: Add AMD Seattle SoC EDAC To: Borislav Petkov , Hanjun Guo References: <1445282597-18999-1-git-send-email-brijeshkumar.singh@amd.com> <20151019205236.GB453@leverpostej> <56266F7E.6030404@amd.com> <20151020165744.GE31130@pd.tnic> <20151020172654.GC4943@leverpostej> <20151020173639.GH31130@pd.tnic> <5626F09F.4050107@huawei.com> <20151021093536.GA3575@pd.tnic> Cc: Mark Rutland , Brijesh Singh , Arnd Bergmann , linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, dougthompson@xmission.com, mchehab@osg.samsung.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Huxinwei From: Andre Przywara X-Enigmail-Draft-Status: N1110 Organization: ARM Ltd. Message-ID: <5627627A.9010906@arm.com> Date: Wed, 21 Oct 2015 11:01:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <20151021093536.GA3575@pd.tnic> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 21/10/15 10:35, Borislav Petkov wrote: > On Wed, Oct 21, 2015 at 09:55:43AM +0800, Hanjun Guo wrote: >> So I think the meaning of those error register is the same, but the way >> of handle it may different from SoCs, for single bit error: >> >> - SoC may trigger a interrupt; >> - SoC may just keep silent so we need to scan the registers using poll >> mechanism. >> >> For Double bit error: >> - SoC may also keep silent >> - Trigger a interrupt >> - Trigger a SEI (system error) >> >> Any suggestion to cover those cases? > > Well, I guess we can implement all those and have them configurable > in the sense that a single driver loads, it has all functionality and > dependent on the vendor detection, it does only what the vendor wants > like trigger an interrupt or remain silent or ... I guess the firmware (running in EL3) will take precedence over this driver anyway, so we could just optimistically implement all errors, as the driver will just never see errors that are handled in firmware (?) In case of a critical error for instance I expect the firmware to never return to EL1. > > Btw, in talking about this with Andre last night, he had the suggestion > that this functionality is also in other implementations besides A57 so > maybe the driver should be called arm_cortex_edac... Yeah, so looking at the A-72 and the A-53 TRM I see those registers to be there as well. The A-72 and the A-57 versions look identical to me, the A-53 version is only slightly different, but apparently still compatible. So I'd suggest to let this driver load on detecting all three MIDRs. Should later revisions of any of those parts change the register meaning, we could add a blacklist or specific MIDR detection. But let's just not assume the worst in the first place ;-) Cheers, Andre.