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Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI
To: Maxime Ripard <maxime.ripard@free-electrons.com>
References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com>
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Cc: Jean-Francois Moine <moinejf@free.fr>, devicetree@vger.kernel.org,
        Vishnu Patekar <vishnupatekar0510@gmail.com>,
        =?UTF-8?Q?Emilio_L=c3=b3pez?= <emilio@elopez.com.ar>,
        Michael Turquette <mturquette@baylibre.com>,
        linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
        Hans de Goede <hdegoede@redhat.com>, Chen-Yu Tsai <wens@csie.org>,
        Rob Herring <robh+dt@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-arm-kernel@lists.infradead.org
From: Jens Kuske <jenskuske@gmail.com>
Message-ID: <5628C8E2.6040703@gmail.com>
Date: Thu, 22 Oct 2015 13:30:42 +0200
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On 22/10/15 11:14, Maxime Ripard wrote:
> On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote:
>> On Thu, 22 Oct 2015 10:47:35 +0200
>> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
>>
>>> Not really. The uart0 reset is the bit 16, in the reset register 4.
>>>
>>> 4 * 32 + 16 = 44.
>>>
>>> Not 112, but still not 208 either.
>>
>> The registers are numbered 1..5, then
>>
>> (4 - 1) * 32 + 16 = 112
> 
> Not on my version, and even then, UARTs are on the last reset
> register, which would still make 144.
> 
> Maxime
> 

There are holes between reg2 and reg3 and reg4 for some reason, but even
if we would correct that with some of_xlate() function they won't
completely line up with the gates.

Jens