From: Siddhesh Poyarekar <sid@reserved-bit.com>
To: "Suzuki K. Poulose" <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will.deacon@arm.com,
mark.rutland@arm.com, dave.martin@arm.com,
Vladimir.Murzin@arm.com, steve.capper@linaro.org,
linux-kernel@vger.kernel.org, ard.biesheuvel@linaro.org,
james.morse@arm.com, marc.zyngier@arm.com,
christoffer.dall@linaro.org, andre.przywara@arm.com,
edward.nevill@linaro.org, aph@redhat.com, ryan.arnold@linaro.org
Subject: Re: [PATCH v3 00/24] arm64: Consolidate CPU feature handling
Date: Sun, 25 Oct 2015 13:36:00 +0530 [thread overview]
Message-ID: <562C8D68.9040008@reserved-bit.com> (raw)
In-Reply-To: <1444756952-31145-1-git-send-email-suzuki.poulose@arm.com>
On Tuesday 13 October 2015 10:52 PM, Suzuki K. Poulose wrote:
> Apart from the selected feature registers, we expose MIDR_EL1 (Main
> ID Register). The user should be aware that, reading MIDR_EL1 can be
> tricky on a heterogeneous system (just like getcpu()). We export the
> value of the current CPU where 'MRS' is executed. REVIDR is not exposed
> via MRS, since we cannot guarantee atomic access to both MIDR and REVIDR
> (task migration). So they both are exposed via sysfs under :
>
> /sys/devices/system/cpu/cpu$ID/identification/
> \- midr
> \- revidr
>
> The ABI useful for the toolchains (e.g, gcc, dynamic linker, JIT) to make
> better runtime decisions based on what is available.
Thank you for doing this. I'm prototyping glibc support to select
optimal functions by micro-architecture and I had a couple of concerns.
The midr emulation may not be sufficient for glibc to select optimal
routines because there could theoretically be sufficient variance
between cpus with only different revidr that vendors may write different
optimal routines. Secondly, on a heterogeneous system, we won't be able
to select a routine reliably using just the emulated instruction since
we have no control where it runs and we would want to know what each of
the cpus looks like.
The sysfs API solves this problem, but it doesn't seem like an optimal
thing to do in an IFUNC resolver in glibc. CPU information is scattered
in 2*N+1 files for N processor cores. This means for every process, one
has to make 4*N+2 system calls to simply read in this information and
cache it for later decision making. On a 64 core system, this would
mean making 258 additional system calls from within the IFUNC resolver,
which seems quite excessive.
Would you be able to consolidate all cpu identification into a single
file? This would allow glibc to just map in the file and read in all of
the information in one go, greatly reducing the number of syscalls.
The other alternative I was thinking of was to have an additional hwcap
HWCAP_HETEROGENEOUS_CPU which is set if there are different kinds of
processor cores in the system, but that will force us to stick to
default routines for heterogeneous cores.
Siddhesh
next prev parent reply other threads:[~2015-10-25 8:15 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-13 17:22 [PATCH v3 00/24] arm64: Consolidate CPU feature handling Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 01/24] arm64: Make the CPU information more clear Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 02/24] arm64: Delay ELF HWCAP initialisation until all CPUs are up Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 03/24] arm64: Delay cpuinfo_store_boot_cpu Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 04/24] arm64: Move cpu feature detection code Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 05/24] arm64: Move mixed endian support detection Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 06/24] arm64: Move /proc/cpuinfo handling code Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 07/24] arm64: Define helper for sys_reg id manipulation Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 08/24] arm64: Handle width of a cpuid feature Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 09/24] arm64: Keep track of CPU feature registers Suzuki K. Poulose
2015-10-15 10:36 ` Catalin Marinas
2015-10-15 10:45 ` Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 10/24] arm64: Consolidate CPU Sanity check to CPU Feature infrastructure Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 11/24] arm64: Read system wide CPUID value Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 12/24] arm64: Cleanup mixed endian support detection Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 13/24] arm64: Populate cpuinfo after notify_cpu_starting Suzuki K. Poulose
2015-10-15 10:54 ` Catalin Marinas
2015-10-15 13:23 ` Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 14/24] arm64: Delay cpu feature capability checks Suzuki K. Poulose
2015-10-17 22:56 ` kbuild test robot
2015-10-19 9:41 ` Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 15/24] arm64: Make use of system wide " Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 16/24] arm64: Cleanup HWCAP handling Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 17/24] arm64: Move FP/ASIMD hwcap handling to common code Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 18/24] arm64/debug: Make use of the system wide safe value Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 19/24] arm64/kvm: Make use of the system wide safe values Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 20/24] arm64: Documentation - Expose CPU feature registers Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 21/24] arm64: Add helper to decode register from instruction Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 22/24] arm64: cpufeature: Track the user visible fields Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 23/24] arm64: Expose feature registers by emulating MRS Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 24/24] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Suzuki K. Poulose
2015-10-14 9:03 ` Suzuki K. Poulose
2015-10-16 15:13 ` [PATCH v3 00/24] arm64: Consolidate CPU feature handling Dave Martin
2015-10-16 15:32 ` Suzuki K. Poulose
2015-10-16 15:42 ` Dave Martin
2015-10-25 8:06 ` Siddhesh Poyarekar [this message]
2015-10-27 18:09 ` Suzuki K. Poulose
2015-10-28 8:53 ` Siddhesh Poyarekar
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