From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753294AbbJZH1y (ORCPT ); Mon, 26 Oct 2015 03:27:54 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:2106 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752604AbbJZH1w (ORCPT ); Mon, 26 Oct 2015 03:27:52 -0400 Message-ID: <562DD5D2.9000705@hisilicon.com> Date: Mon, 26 Oct 2015 15:27:14 +0800 From: Zhou Wang User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 To: Bjorn Helgaas CC: Gabriele Paoloni , Bjorn Helgaas , "jingoohan1@gmail.com" , "pratyush.anand@gmail.com" , Arnd Bergmann , "linux@arm.linux.org.uk" , "thomas.petazzoni@free-electrons.com" , "lorenzo.pieralisi@arm.com" , "james.morse@arm.com" , "Liviu.Dudau@arm.com" , "jason@lakedaemon.net" , "robh@kernel.org" , "gabriel.fernandez@linaro.org" , "Minghuan.Lian@freescale.com" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , zhangjukuo , qiuzhenfa , "liudongdong (C)" , qiujiang , "xuwei (O)" , "Liguozhu (Kenneth)" Subject: Re: [PATCH v11 1/6] PCI: designware: move calculation of bus addresses to DRA7xx References: <1444991021-109306-1-git-send-email-wangzhou1@hisilicon.com> <1444991021-109306-2-git-send-email-wangzhou1@hisilicon.com> <20151021221524.GM1583@localhost> <20151022163534.GB21237@localhost> In-Reply-To: <20151022163534.GB21237@localhost> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.66.65.131] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.562DD5EB.005E,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8afa063b61169e54f8d6e89763beb69c Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015/10/23 0:35, Bjorn Helgaas wrote: > Hi Gabriele, > > On Thu, Oct 22, 2015 at 07:21:41AM +0000, Gabriele Paoloni wrote: >>> -----Original Message----- >>> From: Bjorn Helgaas [mailto:helgaas@kernel.org] > >>>> #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C >>>> #define LINK_UP BIT(16) >>>> +#define CPU_TO_BUS_ADDR 0x0FFFFFFF >>> >>> "CPU_TO_BUS_ADDR" is a very generic name. Since you do have DRA7XX in >>> other #defines and static symbols in this file, maybe it could be DRA7XX to >>> make it obvious that it only applies here? >> >> Ok will change to DRA7XX_CPU_TO_BUS_ADRR in v12 >> .. > >>>> + if (pp->io_mod_base) >>>> + pp->io_mod_base &= CPU_TO_BUS_ADDR; >>> >>> These are equivalent to >>> >>> pp->io_mod_base &= CPU_TO_BUS_ADDR; >>> >>> (You don't need to test whether they're zero first.) >> >> Yes agreed, will change in v12 >> ... > >>>> cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); >>>> @@ -415,8 +411,7 @@ int dw_pcie_host_init(struct pcie_port *pp) >>>> pp->io_base = range.cpu_addr; >>>> >>>> /* Find the untranslated IO space address */ >>>> - pp->io_mod_base = of_read_number(parser.range - >>>> - parser.np + na, ns); >>>> + pp->io_mod_base = range.cpu_addr; >>> >>> So apparently >>> >>> "of_read_number() == range.cpu_addr & CPU_TO_BUS_ADDR" on DRA7xx >>> "of_read_number() == range.cpu_addr" everywhere else? >> >> Yes correct >> >>> Is that right? Is that a valid assumption, i.e., are we assuming >>> anything about DTs in the field that we shouldn't? >> >> Before I wrote a patch that was generic to accommodate intermediate level >> of translation between PCI_addr -> BUS_addr -> CPU_addr >> >> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/360922.html >> >> After discussion we agreed to solve it with a bitmask rather than adding >> a field to of_pci_range to make it generic. >> The bitmask only applies to DRA7xx > > I haven't gotten all the way through this series yet, but don't bother with > a v12 just for these minor changes. I can easily fix them up when applying > it. > > Bjorn > Hi Gabriele and Bjorn, Sorry for late, I am preparing v12 patchset and I will fix above problems together with other patches. Many thanks, Zhou > . >