From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79BD5C04AB3 for ; Wed, 29 May 2019 08:07:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D0CD2081C for ; Wed, 29 May 2019 08:07:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726532AbfE2IHA (ORCPT ); Wed, 29 May 2019 04:07:00 -0400 Received: from gloria.sntech.de ([185.11.138.130]:48014 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725895AbfE2IHA (ORCPT ); Wed, 29 May 2019 04:07:00 -0400 Received: from ip5f5a6320.dynamic.kabel-deutschland.de ([95.90.99.32] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1hVtbm-0002wf-P7; Wed, 29 May 2019 10:06:50 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Jianqun Xu Cc: mark.rutland@arm.com, robh+dt@kernel.org, zhangzj@rock-chips.com, manivannan.sadhasivam@linaro.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs Date: Wed, 29 May 2019 10:06:50 +0200 Message-ID: <5655934.Q7EnKghNLn@diego> In-Reply-To: <20190529074752.19388-1-jay.xu@rock-chips.com> References: <20190528044850.23703-1-jay.xu@rock-chips.com> <20190529074752.19388-1-jay.xu@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jay, Am Mittwoch, 29. Mai 2019, 09:47:52 CEST schrieb Jianqun Xu: > This patch adds core dtsi file for Rockchip RK3399Pro SoCs, > include rk3399.dtsi. Also enable these nodes: > - pcie/pcie_phy > - sdhci/sdio/emmc/sdmmc > > Signed-off-by: Jianqun Xu > --- > changes since v1: > - remove dfi and dmc > > arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > new file mode 100644 > index 000000000000..b6d433ffa67d > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. > + > +#include "rk3399.dtsi" > + > +/ { > + compatible = "rockchip,rk3399pro"; > + > + xin32k: xin32k { > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "xin32k"; > + #clock-cells = <0>; > + }; Just to clarify, is the x32k clock really part of the soc itself? Like on older SoCs it was always supplied from the pmic or a separate rtc chip. > +}; > + > +&emmc_phy { > + status = "okay"; > +}; Is the emmc used inside the soc? As otherwise emmc / mmc controller settings would be more a part of the actual board using the soc. > +&pcie_phy { > + status = "okay"; > +}; > + > +&pcie0 { > + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; > + num-lanes = <4>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_clkreqn_cpm>; > + status = "okay"; > +}; This is probably needed as it needs to talk the rk1808 part over pcie, so it's really internal to the soc. > + > +&sdhci { > + bus-width = <8>; > + mmc-hs400-1_8v; > + supports-emmc; > + non-removable; > + keep-power-in-suspend; > + mmc-hs400-enhanced-strobe; > + status = "okay"; > +}; Same comment as for emmc_phy above > +&sdio0 { > + clock-frequency = <150000000>; > + clock-freq-min-max = <200000 150000000>; > + supports-sdio; > + bus-width = <4>; > + disable-wp; > + cap-sd-highspeed; > + cap-sdio-irq; > + keep-power-in-suspend; > + mmc-pwrseq = <&sdio_pwrseq>; > + non-removable; > + num-slots = <1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; > + sd-uhs-sdr104; > + status = "okay"; > +}; Same comment as for emmc_phy above > +&sdmmc { > + clock-frequency = <150000000>; > + clock-freq-min-max = <400000 150000000>; > + supports-sd; > + bus-width = <4>; > + cap-mmc-highspeed; > + cap-sd-highspeed; > + disable-wp; > + num-slots = <1>; > + vqmmc-supply = <&vccio_sd>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; > + status = "okay"; > +}; Same comment as for emmc_phy above